TMS27C210A 65536 BY 16BIT UV ERASABLE

TMS27PC210A 65536 BY 16BIT

PROGRAMMABLE READONLY MEMORIES

SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

8

POST OFFICE BOX 655303

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VOH High-level dc output voltage

IOH = − 20 µA

VCC −0.2

V

VOH High-level dc output voltage

IOH = − 2 mA

2.4

V

VOL

Low-level dc output voltage

IOL = 2.1 mA

0.4

V

VOL

Low-level dc output voltage

IOL = 20 µA

0.1

V

II

Input current (leakage)

VI = 0 V to 5.5 V

±1

µA

IO

Output current (leakage)

VO = 0 V to VCC

±1

µA

IPP1 VPP supply current

VPP = VCC = 5.5 V

10

µA

IPP2 VPP supply current (during program pulse)

VPP = 13 V

50

mA

ICC1 VCC supply current (standby)

TTL-input level

VCC = 5.5 V,

E = VIH

500

µA

ICC1 VCC supply current (standby)

CMOS-input level

VCC = 5.5 V,

E = VCC

100

µA

ICC2 VCC supply current (active)

VCC = 5.5 V,

E = VIL,

tcycle = minimum cycle time,

outputs open†

50

mA

† Minimum cycle time = maximum address access time.

capacitance

over

recommended

ranges

of

supply

voltage

and

operating

free-air

PARAMETER

TEST CONDITIONS

MIN

TYP§

MAX

UNIT

CI

Input capacitance

VI = 0 V,

f = 1 MHz

8

12

pF

CO

Output capacitance

VO = 0 V, f = 1 MHz

12

15

pF

‡ Capacitance measurements are made on a sample basis only.

§ Typical values are at TA = 25°C and nominal voltages.

switching characteristics over full ranges of recommended operating conditions (see Notes 3

and 4)

PARAMETER

TEST

CONDITIONS

’27C210A-10

’27PC210A-10

’27C210A-12

’27PC210A-12

’27C210A-15

’27PC210A-15

’27C210A-20

’27PC210A-20

’27C210A-25

’27PC210A-25

UNIT

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)

Access time from

address

100

120

150

200

250

ns

ta(E)

Access time from

chip enable

100

120

150

200

250

ns

ten(G)

Output enable

time from G

CL = 100 pF,

1 Series 74

55

55

75

75

100

ns

tdis

Output disable

time from G or E,

whichever occurs

first¶

1 Series 74

TTL load,

Input tr ≤ 20 ns,

Input tf ≤ 20 ns

0

50

0

50

0

60

0

60

0

60

ns

tv(A)

Output data valid

time after change

of address, E, or

G, whichever

occurs first¶

0

0

0

0

0

ns

¶ Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.

NOTES:

3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low (see Figure 2).

4. Common test conditions apply for tdis except during programming.