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TMS320C6671 Datasheet(PDF) 8 Page - Texas Instruments

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Part # TMS320C6671
Description  Fixed and Floating-Point Digital Signal Processor
Download  238 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TMS320C6671 Datasheet(HTML) 8 Page - Texas Instruments

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TMS320C6671
SPRS756E—November 2010—Revised March 2014
8
Contents
Copyright 2014 Texas Instruments Incorporated
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7.6.3
Main PLL Control Register . . . . . . . . . . . . . . . . . . . . 147
7.6.4
Main PLL and PLL Controller Initialization
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.6.5
Main PLL Controller/SRIO/HyperLink/PCIe
Clock Input Electrical Data/Timing . . . . . . . . . . . 148
7.7
DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.7.1
DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . 150
7.7.2
DDR3 PLL Device-Specific Information . . . . . . . . 151
7.7.3
DDR3 PLL Initialization Sequence. . . . . . . . . . . . . 151
7.7.4
DDR3 PLL Input Clock Electrical Data/Timing. . 152
7.8
PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.8.1
PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . 153
7.8.2
PASS PLL Device-Specific Information . . . . . . . . 154
7.8.3
PASS PLL Initialization Sequence . . . . . . . . . . . . . 154
7.8.4
PASS PLL Input Clock Electrical Data/Timing . . 155
7.9
Enhanced Direct Memory Access (EDMA3)
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.9.1
EDMA3 Device-Specific Information . . . . . . . . . . 157
7.9.2
EDMA3 Channel Controller Configuration . . . . 157
7.9.3
EDMA3 Transfer Controller Configuration. . . . . 157
7.9.4
EDMA3 Channel Synchronization Events. . . . . . 158
7.10
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.10.1
Interrupt Sources and Interrupt Controller . . . 162
7.10.2
CIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.10.3
Inter-Processor Register Map. . . . . . . . . . . . . . . . 181
7.10.4
NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.10.5
External Interrupts Electrical Data/Timing . . . 183
7.10.6
Host Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . 183
7.11
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . 184
7.11.1
MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.11.2
MPU Programmable Range Registers . . . . . . . . 192
7.12
DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.12.1
DDR3 Memory Controller Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.12.2
DDR3 Memory Controller Race Condition
Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.12.3
DDR3 Memory Controller Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
7.13
I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
7.13.1
I2C Device-Specific Information . . . . . . . . . . . . . .199
7.13.2
I2C Peripheral Register Description(s) . . . . . . . .200
7.13.3
I2C Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .201
7.14
SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
7.14.1
SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .204
7.15
HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
7.15.1
HyperLink Device-Specific Interrupt Event. . . .207
7.15.2
HyperLink Electrical Data/Timing . . . . . . . . . . . .209
7.16
UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.17
PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
7.18
TSIP Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
7.18.1
TSIP Electrical Data/Timing . . . . . . . . . . . . . . . . . .213
7.19
EMIF16 Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
7.19.1
EMIF16 Electrical Data/Timing . . . . . . . . . . . . . . .215
7.20
Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
7.21
Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
7.22
Gigabit Ethernet (GbE) Switch Subsystem. . . . . . . . . .218
7.23
Management Data Input/Output (MDIO) . . . . . . . . . .220
7.24
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
7.24.1
Timers Device-Specific Information . . . . . . . . . .221
7.24.2
Timers Electrical Data/Timing . . . . . . . . . . . . . . . .222
7.25
Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . .222
7.26
General-Purpose Input/Output (GPIO) . . . . . . . . . . . . .223
7.26.1
GPIO Device-Specific Information . . . . . . . . . . . .223
7.26.2
GPIO Electrical Data/Timing. . . . . . . . . . . . . . . . . .223
7.27
Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
7.28
Emulation Features and Capability . . . . . . . . . . . . . . . .224
7.28.1
Advanced Event Triggering (AET) . . . . . . . . . . . .224
7.28.2
Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
7.28.3
IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
8
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
9
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
9.1
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
9.2
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233


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