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TPS62321YZDT Datasheet(PDF) 5 Page - Texas Instruments |
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TPS62321YZDT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 31 page www.ti.com PIN ASSIGNMENTS ADJ FB AVIN EN AGND SW VIN MODE/SYNC PGND VOUT VIN NC NC AVIN EN AGND SW MODE/SYNC PGND VOUT ADJ A1 B1 C1 D1 A2 B2 C2 D2 GND SW MODE/SYNC VOUT VIN EN FB MODE/SYNC C1 A2 B2 C2 D2 A1 B1 D1 VIN EN ADJ FB GND SW VOUT TPS62300, TPS62320 QFN-10 (TOP VIEW) TPS6230x, TPS6232x FIXED OUTPUT VOLTAGE (QFN-10) (TOP VIEW) TPS6230x, TPS6231x, TPS6232x CSP-8 (TOP VIEW) TPS6230x, TPS6231x, TPS6232x CSP-8 (BOTTOM VIEW) TPS62300, TPS62301, TPS62302 TPS62303, TPS62305, TPS62311 TPS62313, TPS62320, TPS62321 SLVS528B – JULY 2004 – REVISED JUNE 2005 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NO. NO. NAME QFN CSP VIN 1 A2 I Supply voltage for output power stage. AVIN 2 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor. This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown EN 3 B2 I mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be terminated. This is the internal reference voltage used to regulate VO. This pin is not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect ADJ pin on fixed output voltage version of TPS6230xYZD, TPS6231xYZD and TPS6232xYxD. ADJ 4 C2 I/O On TPS62300 and TPS62320, this pin can also be used as an external control input. The output voltage is 1.5x the applied voltage at ADJ. This is the feedback pin of the device. For the adjustable version, an external resistor divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. This pin is FB 5 D2 I not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect the FB pin on the fixed output voltage version of TPS6230xYZD, TPS6231xYZD and TPS6232xYxD. VOUT 6 D1 I Output feedback sense input. Connect VOUT to the converter’s output. AGND 7 Analog ground. Connect to PGND via the PowerPAD™ underneath IC. Input for synchronization to external clock signal. This pin must not be left floating and must be terminated. Synchronizes the converter switching frequency to an external clock signal MODE/SYNC = LOW (GND): The device is operating in fixed frequency pulse width modulation MODE/SYNC 8 C1 I mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. MODE/SYNC = HIGH (VIN): Low-noise mode enabled, fixed frequency PWM operation forced. PGND 9 A1 Power ground. This is the switch pin of the converter and is connected to the drain of the internal Power SW 10 B1 I/O MOSFETs. PowerPAD™ N/A Internally connected to PGND. 5 |
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