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TMS320VC5410AGGU12 Datasheet(PDF) 9 Page - Texas Instruments

Part # TMS320VC5410AGGU12
Description  Fixed-Point Digital Signal Processor
Download  99 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320VC5410AGGU12 Datasheet(HTML) 9 Page - Texas Instruments

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TMS320VC5410A Features
TMS320VC5410A
Fixed-Point Digital Signal Processor
www.ti.com
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Parallel Load
• Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One
• Conditional Store Instructions
Program Memory Bus
• Fast Return From Interrupt
• 40-Bit Arithmetic Logic Unit (ALU) Including a
• On-Chip Peripherals
40-Bit Barrel Shifter and Two Independent
Software-Programmable Wait-State
40-Bit Accumulators
Generator and Programmable
• 17- × 17-Bit Parallel Multiplier Coupled to a
Bank-Switching
40-Bit Dedicated Adder for Non-Pipelined
On-Chip Programmable Phase-Locked
Single-Cycle Multiply/Accumulate (MAC)
Loop (PLL) Clock Generator With Internal
Operation
Oscillator or External Clock Source(1)
One 16-Bit Timer
• Compare, Select, and Store Unit (CSSU) for the
Six-Channel Direct Memory Access (DMA)
Add/Compare Selection of the Viterbi Operator
Controller
• Exponent Encoder to Compute an Exponent
Three Multichannel Buffered Serial Ports
Value of a 40-Bit Accumulator Value in a
(McBSPs)
Single Cycle
8/16-Bit Enhanced Parallel Host-Port
• Two Address Generators With Eight Auxiliary
Interface (HPI8/16)
Registers and Two Auxiliary Register
• Power Consumption Control With IDLE1,
Arithmetic Units (ARAUs)
IDLE2, and IDLE3 Instructions With
• Data Bus With a Bus Holder Feature
Power-Down Modes
• Extended Addressing Mode for 8M × 16-Bit
• CLKOUT Off Control to Disable CLKOUT
Maximum Addressable External Program
• On-Chip Scan-Based Emulation Logic, IEEE
Space
Std 1149.1(2) (JTAG) Boundary Scan Logic
• 64K × 16-Bit On-Chip RAM Composed of Eight
• 144-Pin Ball Grid Array (BGA) (GGU Suffix)
Blocks of 8K
× 16-Bit On-Chip Dual-Access
• 144-Pin Low-Profile Quad Flatpack (LQFP)
Program/Data RAM
(PGE Suffix)
• 16K × 16-Bit On-Chip ROM Configured for
• 6.25-ns Single-Cycle Fixed-Point Instruction
Program Memory
Execution Time (160 MIPS)
• Enhanced External Parallel Interface (XIO2)
• 8.33-ns Single-Cycle Fixed-Point Instruction
• Single-Instruction-Repeat and Block-Repeat
Execution Time (120 MIPS)
Operations for Program Code
• 3.3-V I/O Supply Voltage (160 and 120 MIPS)
• Block-Memory-Move Instructions for Better
• 1.6-V Core Supply Voltage (160 MIPS)
Program and Data Management
• 1.5-V Core Supply Voltage (120 MIPS)
• Instructions With a 32-Bit Long Word Operand
(1)
The on-chip oscillator is not available on all 5410A devices.
• Instructions With Two- or Three-Operand
For applicable devices, see the TMS320VC5410A Digital
Reads
Signal Processor Silicon Errata (literature number SPRZ187).
(2)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and
• Arithmetic Instructions With Parallel Store and
Boundary Scan Architecture.
TMS320C54x, MicroStar BGA, TMS320C54x, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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