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TMS320VC5416GGU160 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320VC5416GGU160 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 98 page  1 TMS320VC5416 Features TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 Reads • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One • Arithmetic Instructions With Parallel Store and Program Memory Bus Parallel Load • 40-Bit Arithmetic Logic Unit (ALU) Including a • Conditional Store Instructions 40-Bit Barrel Shifter and Two Independent • Fast Return From Interrupt 40-Bit Accumulators • On-Chip Peripherals • 17- × 17-Bit Parallel Multiplier Coupled to a – Software-Programmable Wait-State 40-Bit Dedicated Adder for Non-Pipelined Generator and Programmable Single-Cycle Multiply/Accumulate (MAC) Bank-Switching Operation – On-Chip Programmable Phase-Locked • Compare, Select, and Store Unit (CSSU) for the Loop (PLL) Clock Generator With External Add/Compare Selection of the Viterbi Operator Clock Source – One 16-Bit Timer • Exponent Encoder to Compute an Exponent – Six-Channel Direct Memory Access (DMA) Value of a 40-Bit Accumulator Value in a Controller Single Cycle – Three Multichannel Buffered Serial Ports • Two Address Generators With Eight Auxiliary (McBSPs) Registers and Two Auxiliary Register – 8/16-Bit Enhanced Parallel Host-Port Arithmetic Units (ARAUs) Interface (HPI8/16) • Data Bus With a Bus Holder Feature • Power Consumption Control With IDLE1, • Extended Addressing Mode for 8M × 16-Bit IDLE2, and IDLE3 Instructions With Maximum Addressable External Program Power-Down Modes Space • CLKOUT Off Control to Disable CLKOUT • 128K × 16-Bit On-Chip RAM Composed of: • On-Chip Scan-Based Emulation Logic, IEEE – Eight Blocks of 8K × 16-Bit On-Chip Std 1149.1 (JTAG) Boundary Scan Logic(1) Dual-Access Program/Data RAM • 144-Pin Ball Grid Array (BGA)(GGU Suffix) – Eight Blocks of 8K × 16-Bit On-Chip Single-Access Program RAM • 144-Pin Low-Profile Quad Flatpack (LQFP)(PGE Suffix) • 16K × 16-Bit On-Chip ROM Configured for Program Memory • 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS) • Enhanced External Parallel Interface (XIO2) • 8.33-ns Single-Cycle Fixed-Point Instruction • Single-Instruction-Repeat and Block-Repeat Execution Time (120 MIPS) Operations for Program Code • 3.3-V I/O Supply Voltage (160 and 120 MIPS) • Block-Memory-Move Instructions for Better Program and Data Management • 1.6-V Core Supply Voltage (160 MIPS) • Instructions With a 32-Bit Long Word Operand • 1.5-V Core Supply Voltage (120 MIPS) (1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and • Instructions With Two- or Three-Operand Boundary Scan Architecture TMS320C54x, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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