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TMX5700914APZQQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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TMX5700914APZQQ1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 159 page  TMS570LS0914 www.ti.com SPNS225C – JUNE 2013 – REVISED SEPTEMBER 2015 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPNS225B device-specific data manual to make it an SPNS225C revision. Scope: Applicable updates to the TMS570LS09114 device family, specifically relating to the TMS570LS0914 devices (Silicon Revision A), which are now in the production data (PD) stage of development have been incorporated. Changes from November 13, 2014 to September 15, 2015 (from B Revision (November 2014) to C Revision) Page • Section 1.1 (Features): Updated/Changed the N2HET feature ................................................................. 1 • Section 1.1: Removed ZWT package; no longer supported [along with ZWT performance characteristics] ............ 1 • Section 1.3 (Description): Corrected DMA description, 32 peripheral requests, not 32 control packets .................. 4 • Section 1.3: Updated/Changed ESM paragraph ................................................................................. 4 • Table 3-1 (TMS570LS0914 Device Comparison): Updated/Changed the GPIO pin count for PZ package devices from "55" to "45" ...................................................................................................................... 9 • Section 4.2 (Signal Descriptions): Updated/Changed "Default Pull Type" to "Reset Pull Type" .......................... 12 • Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Updated/Changed N2HET1 time input capture or output compare pin description ................................................................................................ 14 • Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description ........................... 14 • Table 4-5 (PGE Enhanced Pulse-Width Modulator Modules (ePWM)): Updated/Changed EPWM1SYNCI ............ 16 • Table 4-15 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description ........................ 21 • Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Updated/Changed N2HET1 time input capture or output compare pin description .................................................................................................... 23 • Table 4-23 (PZ Enhanced Pulse-Width Modulator Modules (ePWM)): Updated/Changed EPWM1SYNCI ............. 24 • Table 4-32 (PZ Test and Debug Modules Interface): Updated/Changed TEST pin description .......................... 29 • Table 4-41 (Selectable 8mA/2mA Control): ...................................................................................... 36 • Section 5.1 (Absolute Maximum Ratings): Moved Storage temperature range back to Absolute Maximum Ratings table. ........................................................................................................................ 37 • Section 5.3 (Power-On Hours (POH)): Added associated footnotes ......................................................... 37 • Updated/Changed Section 5.5, Input/Output Electrical Characteristics - changed UNIT for Input Current (I/O pins) from mA to µA ................................................................................................................ 39 • Section 5.6 (Power Consumption Over Recommended Operating Conditions): Updated/Changed I CC TYP and MAX values .......................................................................................................................... 40 • Section 5.7 (Thermal Resistance Characteristics): Added new section ..................................................... 41 • Table 5-1 (Thermal Resistance Characteristics (PGE Package)): Added R ΘJA test conditions and added ΨJT ....... 41 • Table 5-2 (Thermal Resistance Characteristics (PZ Package)): Added R ΘJA test conditions and added ΨJT.......... 41 • Section 5.8.1.2 (Wait States Required): Updated/Changed "The TCM flash can support ..." paragraph ............... 43 • Section 6.1 (Device Power Domains): Updated/Changed the core power domains count to "5" ......................... 44 • Section 6.1: Deleted "The logic in the modules ..." NOTE, no longer applicable ........................................... 44 • Table 6-1 (Voltage Monitoring Specifications): Updated/Changed the VMON, VCC low MAX from "1.0" to "1.13" V... 44 • Table 6-4 (Electrical Requirements for nPORRST): Updated/Changed tf(nPORRST) MIN from "500" to "475" ns......... 46 • Table 6-6 (nRST Timing Requirements): Updated/Changed tv(RST) number of cycles from " 2252tc(OSC)" to "2256tc(OSC)" .......................................................................................................................... 47 • Table 6-6: Updated/Changed tf(nRST) MIN from "500" to "475" ns ............................................................. 47 • Section 6.5.1 Added Quantity of Breakpoints and Watchpoints .............................................................. 48 • Table 6-10 (LPO Specifications): Updated/Changed LPO - HF oscillator, untrimmed frequency TYP value from "9.6" to "9" MHz ..................................................................................................................... 53 • Table 6-10: Added LPO - HF oscillator, trimmed frequency MIN/TYP/MAX values ........................................ 53 • Table 6-19 (Glitch Filter Timing Specifications): Updated/Changed nRST, nPORRST, and TEST MIN values from "500" to "475" ns .............................................................................................................. 60 • Table 6-23 (Timing Requirements for Program Flash): Added footnote to terase(bank0), Sector/Bank erase time ........ 68 • Table 6-25 (PBIST RAM Grouping): Added table notes identifying address ranges of ESRAM PBIST groups ........ 71 • Table 6-25: Added missing values for PBIST_ROM and STC_ROM ........................................................ 71 • Table 6-32 (Reset/Abort/Error Sources): Added POWER DOMAIN CONTROL rows .................................... 85 • Section 6.20.3 (JTAG Identification Code): Added Table 6-34, JTAG ID Code ............................................ 88 Copyright © 2013–2015, Texas Instruments Incorporated Revision History 7 Submit Documentation Feedback Product Folder Links: TMS570LS0914 |
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