TMS44400, TMS44400P, TMS46400, TMS46400P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS562C – MAY 1995 – REVISED NOVEMBER 1996

1

POST OFFICE BOX 1443

(

±10% Tolerance)

(

±10% Tolerance)

200-

µA CMOS Standby

200-

µA Self Refresh

300-

µA Extended-Refresh Battery

Backup

ACCESS ACCESS ACCESS

READ

TIME

TIME

TIME

OR WRITE

(tRAC)(tCAC)(tAA)

CYCLE

(MAX)

(MAX)

(MAX)

(MIN)

’4x400/P-60

60 ns

15 ns

30 ns

110 ns

’4x400/P-70

70 ns

18 ns

35 ns

130 ns

’4x400/P-80

80 ns

20 ns

40 ns

150 ns

Memory Access

1024-Cycle Refresh in 16 ms

128 ms (MAX) for Low-Power,

Self-Refresh Version ( TMS4x400P)

0

°C to 70°C

AVAILABLE OPTIONS

DEVICE

POWER

SUPPLY

SELF-REFRESH

BATTERY

BACKUP

REFRESH

CYCLES

TMS44400

5 V

—

1024 in 16 ms

TMS44400P

5 V

Yes

1024 in 128 ms

TMS46400

3.3 V

—

1024 in 16 ms

TMS46400P

3.3 V

Yes

1024 in 128 ms

These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines

are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.

The TMS4x400 and TMS4x400P are offered in a 20 / 26-lead plastic small-outline ( TSOP) package ( DGA suffix)

and a 300-mil 20 / 26-lead plastic surface-mount SOJ package ( DJ suffix). Both packages are characterized for

operation from 0

°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

PIN NOMENCLATURE

A0 – A9

Address Inputs

CAS

Column-Address Strobe

DQ1 – DQ4

Data In

OE

Output Enable

RAS

Row-Address Strobe

VCC

5-V or 3.3-V Supply

VSS

Ground

W

Write Enable

DJ PACKAGE

( TOP VIEW )

DQ4

DQ3

CAS

OE

A8

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

DGA PACKAGE

( TOP VIEW )

DQ1

DQ2

W

RAS

A9

A0

A1

A2

A3

DQ4

DQ3

CAS

OE

A8

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

DQ1

DQ2

W

RAS

A9

A0

A1

A2

A3

EPIC is a trademark of Texas Instruments Incorporated.

description

The TMS4x400 series is a set of high-speed,

4 194 304-bit dynamic random-access memories

(DRAMs), organized as 1 048 576 words of four

bits each. The TMS4x400P series is a set of

high-speed,

low-power,

self-refresh

with

extended-refresh,

4 194 304-bit

DRAMs,

organized as 1 048 576 words of four bits each.

Both series employ state-of-the-art enhanced

performance

implanted

CMOS

(EPIC

™)

technology for high performance, reliability, and

low power.

Copyright

© 1996, Texas Instruments Incorporated