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TMS418169-60DZ Datasheet(PDF) 4 Page - Texas Instruments |
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TMS418169-60DZ Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS SMKS886C – MAY1995 – REVISED MARCH 1996 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 operation dual CAS Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins (DQ0 – DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge. All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out (see parameter tCAC) is measured from each individual xCAS to its corresponding DQx pin. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high. For early-write cycles, the data is latched on the first xCAS falling edge. Data is written only into the DQs that have the corresponding xCAS low. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP. extended data out Extended data out (EDO) allows for data-output rates of up to 40 MHz for 60-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time (tRASP). EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains valid for the system to latch the data. After xCAS goes high, the DRAM is decoding the next address. OE and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation benefit. address: A0 – A11 ( TMS416169) and A0 – A9 ( TMS418169) Twenty address bits are required to decode one of the 1 048 576 storage cell locations. For the TMS416169, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched on the chip by the first xCAS. For the TMS418169, 10 row-address bits are set up on A0 – A9 and latched on the chip by RAS. Ten column-address bits are set up on A0 – A9 and latched on the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip-enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip-select, activating its corresponding output buffer and latching the address bits into the column-address buffers. write enable ( W ) The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of OE. This permits early-write operation to be completed with OE grounded. If W goes low in an extended-data-out read cycle, the DQs go into the high-impedance state as long as xCAS is high. data in (DQ0 – DQ15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a |
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