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TMS320F28PLC83PNTR Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320F28PLC83PNTR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 132 page  GPIO Mux DMA Bus DMA Bus 16-bit Peripheral Bus SCI-A/B (4L FIFO) SPI-A/B (4L FIFO) I2C-A (4L FIFO) 32-bit Peripheral Bus ePWM1, ePWM2 HRPWM (2 ch) 32-bit Peripheral Bus eCAP-1 Memory Bus A[1:0] B[1:0] Memory Bus ADC 0-wait Result Regs ADC COMP + DAC COMP1OUT COMP2OUT COMP3OUT Boot-ROM (32Kx16) (0-wait, Non-Secure) DMA 6-ch C28x 32-bit CPU VCU OSC1, OSC2, Ext, PLLs, LPM, WD, CPU Timers0/1/2, PIE TRST TCK, TDI, TMS TDO XCLKIN LPM Wakeup 3 Ext. Interrupts X1 X2 XRS PSWD M0 SARAM (1Kx16) (0-wait, Non-Secure) M1 SARAM (1Kx16) (0-wait, Non-Secure) L5 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM0 L6 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM1 L7 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM2 L8 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM3 L0 DPSARAM (2Kx16) (0-wait, Secure) L1 DPSARAM (1Kx16) (0-wait, Secure) L2 DPSARAM (1Kx16) (0-wait, Secure) L3 DPSARAM (4Kx16) (0-wait, Secure) L4 SARAM (8Kx16) (0-wait, Secure) Code Security Module (CSM) OTP 1Kx16 Secure FLASH 128Kx16 8 equal sectors Secure PUMP OTP/Flash Wrapper 32-bit Peripheral Bus McBSP-A TMS320F28PLC84, TMS320F28PLC83 www.ti.com SPRS802 – SEPTEMBER 2014 1.4 Functional Block Diagram Figure 1-1 shows a functional block diagram of the device. A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2014, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: TMS320F28PLC84 TMS320F28PLC83 |
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