RTL8139C datasheet(39/62 Pages) ETC

Part #	RTL8139C

Description	REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

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RTL8139C(L)

2002/01/10

Rev.1.4

39

Bit

Symbol

Description

15

DPERR

Detected Parity Error: When set indicates that the RTL8139C(L) detected a parity error, even if parity

error handling is disabled in command register PERRSP bit.

14

SSERR

Signaled System Error: When set indicates that the RTL8139C(L) asserted the system error pin, SERRB.

Writing a 1 clears this bit to 0.

13

RMABT

Received Master Abort: When set indicates that the RTL8139C(L) terminated a master transaction with

master abort. Writing a 1 clears this bit to 0.

12

RTABT

Received Target Abort: When set indicates that the RTL8139C(L) master transaction was terminated due

to a target abort. Writing a 1 clears this bit to 0.

11

STABT

Signaled Target Abort: Set to 1 whenever the RTL8139C(L) terminates a transaction with target abort.

Writing a 1 clears this bit to 0.

10-9

DST1-0

Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),

indicating the RTL8139C(L) will assert DEVSELB two clocks after FRAMEB is asserted.

8

DPD

Data Parity error Detected:

This bit sets when the following conditions are met:

• The RTL8139C(L) asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by another

device.

• The RTL8139C(L) operates as a bus master for the operation that caused the error.

• The Command register PERRSP bit is set.

Writing a 1 clears this bit to 0.

7

FBBC

Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operation has no effect.

Config3<FbtBEn>=1, Read as 1.

6

UDF

User Definable Features Supported: Read as 0, write operation has no effect. The RTL8139C(L) does

not support UDF.

5

66MHz

66 MHz Capable: Read as 0, write operation has no effect. The RTL8139C(L) has no 66MHz capability.

4

NewCap

New Capability: Config3<PMEn>=0, Read as 0, write operation has no effect. Config3<PMEn>=1, Read as

1.

0-3

-

Reserved

RID: Revision ID Register

The Revision ID register is an 8-bit register that specifies the RTL8139C(L) controller revision number.

PIFR: Programming Interface Register

The programming interface register is an 8-bit register that identifies the programming interface of the RTL8139C(L)

controller. Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h.

SCR: Sub-Class Register

The Sub-class register is an 8-bit register that identifies the function of the RTL8139C(L). SCR = 00h indicates that the

RTL8139C(L) is an Ethernet controller.

BCR: Base-Class Register

The Base-class register is an 8-bit register that broadly classifies the function of the RTL8139C(L). BCR = 02h indicates

that the RTL8139C(L) is a network controller.

CLS: Cache Line Size

Reads will return a 0, writes are ignored.

LTR: Latency Timer Register

Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8139C(L).

When the RTL8139C(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8139C(L) deasserts FRAMEB

prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8139C(L)

initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is

00H.

HTR: Header Type Register

Reads will return a 0, writes are ignored.

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