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TMS570LS1227ZWT Datasheet(PDF) 1 Page - Texas Instruments |
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TMS570LS1227ZWT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 184 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS570LS1227 SPNS192B – OCTOBER 2012 – REVISED FEBRUARY 2015 TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Automotive-Grade • Enhanced Timing Peripherals for Motor Control Microcontroller for Safety-Critical Applications – 7 Enhanced Pulse Width Modulator (ePWM) – Dual CPUs Running in Lockstep Modules – ECC on Flash and RAM Interfaces – 6 Enhanced Capture (eCAP) Modules – Built-In Self-Test (BIST) for CPU and On-chip – 2 Enhanced Quadrature Encoder Pulse (eQEP) RAMs Modules – Error Signaling Module With Error Pin • Two Next Generation High-End Timer (N2HET) Modules – Voltage and Clock Monitoring – N2HET1: 32 Programmable Channels • ARM® Cortex®-R4F 32-Bit RISC CPU – N2HET2: 18 Programmable Channels – 1.66 DMIPS/MHz With 8-Stage Pipeline – 160-Word Instruction RAM Each With Parity – FPU With Single- and Double-Precision Protection – 12-Region Memory Protection Unit (MPU) – Each N2HET Includes Hardware Angle – Open Architecture With Third-Party Support Generator • Operating Conditions – Dedicated High-End Timer Transfer Unit (HTU) – Up to 180-MHz System Clock for Each N2HET – Core Supply Voltage (VCC): 1.14 to 1.32 V • Two 12-Bit Multibuffered ADC Modules – I/O Supply Voltage (VCCIO): 3.0 to 3.6 V – ADC1: 24 Channels • Integrated Memory – ADC2: 16 Channels Shared With ADC1 – 1.25MB of Program Flash With ECC – 64 Result Buffers Each With Parity Protection – 192KB of RAM With ECC • Multiple Communication Interfaces – 64KB of Flash for Emulated EEPROM With – 10/100 Mbps Ethernet MAC (EMAC) ECC • IEEE 802.3 Compliant (3.3-V I/O Only) • 16-Bit External Memory Interface (EMIF) • Supports MII, RMII, and MDIO • Common Platform Architecture – FlexRay Controller With 2 Channels – Consistent Memory Map Across Family • 8KB of Message RAM With Parity Protection – Real-Time Interrupt (RTI) Timer (OS Timer) • Dedicated FlexRay Transfer Unit (FTU) – 128-Channel Vectored Interrupt Module (VIM) – Three CAN Controllers (DCANs) – 2-Channel Cyclic Redundancy Checker (CRC) • 64 Mailboxes Each With Parity Protection • Direct Memory Access (DMA) Controller • Compliant to CAN Protocol Version 2.0A and – 16 Channels and 32 Control Packets 2.0B – Parity Protection for Control Packet RAM – Inter-Integrated Circuit (I2C) – DMA Accesses Protected by Dedicated MPU – Three Multibuffered Serial Peripheral Interface • Frequency-Modulated Phase-Locked Loop (MibSPI) Modules (FMPLL) With Built-In Slip Detector • 128 Words Each With Parity Protection • Separate Nonmodulating PLL • 8 Transfer Groups • IEEE 1149.1 JTAG, Boundary Scan and ARM – Up to Two Standard Serial Peripheral Interface CoreSight™ Components (SPI) Modules • Advanced JTAG Security Module (AJSM) – Two UART (SCI) Interfaces, One With Local • Calibration Capabilities Interconnect Network (LIN 2.1) Interface – Parameter Overlay Module (POM) Support • 16 General-Purpose Input/Output (GPIO) Pins • Packages Capable of Generating Interrupts – 144-Pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green] 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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