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TMS570LS3135 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS570LS3135 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 170 page  TMS570LS3135, TMS570LS2135, TMS570LS2125 SPNS164C – APRIL 2012 – REVISED APRIL 2015 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.11 Tightly Coupled RAM (TCRAM) Interface Module .. 80 1.1 Features .............................................. 1 6.12 Parity Protection for Peripheral RAMs .............. 80 1.2 Applications ........................................... 2 6.13 On-Chip SRAM Initialization and Testing ........... 82 1.3 Description ............................................ 3 6.14 External Memory Interface (EMIF) .................. 84 1.4 Functional Block Diagram ............................ 5 6.15 Vectored Interrupt Manager ......................... 91 2 Revision History ......................................... 7 6.16 DMA Controller ...................................... 94 3 Device Comparison ..................................... 9 6.17 Real Time Interrupt Module ......................... 96 4 Terminal Configuration and Functions ........... 10 6.18 Error Signaling Module .............................. 98 4.1 PGE QFP Package Pinout (144-Pin) ............... 10 6.19 Reset / Abort / Error Sources ...................... 102 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array) 11 6.20 Digital Windowed Watchdog ....................... 104 4.3 Terminal Functions ................................. 12 6.21 Debug Subsystem ................................. 105 5 Specifications .......................................... 39 7 Peripheral Information and Electrical Specifications ......................................... 116 5.1 Absolute Maximum Ratings ........................ 39 7.1 Peripheral Legend ................................. 116 5.2 ESD Ratings ........................................ 39 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .. 116 5.3 Power-On Hours (POH) ............................. 39 7.3 General-Purpose Input/Output ..................... 127 5.4 Recommended Operating Conditions ............... 40 7.4 Enhanced High-End Timer (N2HET) .............. 128 5.5 Switching Characteristics for Clock Domains ....... 41 7.5 FlexRay Interface .................................. 133 5.6 Wait States Required ............................... 41 7.6 Controller Area Network (DCAN) .................. 135 5.7 Power Consumption ................................. 42 7.7 Local Interconnect Network Interface (LIN) ........ 136 5.8 Input/Output Electrical Characteristics .............. 43 7.8 Serial Communication Interface (SCI) ............. 137 5.9 Thermal Resistance Characteristics ................ 44 7.9 Inter-Integrated Circuit (I2C) ....................... 138 5.10 Output Buffer Drive Strengths ...................... 45 7.10 Multibuffered / Standard Serial Peripheral 5.11 Input Timings ........................................ 46 Interface ............................................ 141 5.12 Output Timings ...................................... 46 8 Device and Documentation Support .............. 153 5.13 Low-EMI Output Buffers ............................ 48 8.1 Device Support ..................................... 153 6 System Information and Electrical 8.2 Documentation Support ............................ 155 Specifications ........................................... 50 8.3 Related Links ...................................... 155 6.1 Device Power Domains ............................. 50 8.4 Community Resources ............................. 155 6.2 Voltage Monitor Characteristics ..................... 51 8.5 Trademarks ........................................ 155 6.3 Power Sequencing and Power On Reset ........... 52 8.6 Electrostatic Discharge Caution ................... 155 6.4 Warm Reset (nRST) ................................. 54 8.7 Glossary ............................................ 155 6.5 ARM-R4F CPU Information ......................... 55 8.8 Device Identification Code Register ............... 157 6.6 Clocks ............................................... 58 8.9 Die Identification Registers ....................... 158 6.7 Clock Monitoring .................................... 66 8.10 Module Certifications ............................... 158 6.8 Glitch Filters ......................................... 68 9 Mechanical Packaging and Orderable 6.9 Device Memory Map ................................ 69 Information ............................................. 165 6.10 Flash Memory ....................................... 77 9.1 Packaging Information ............................. 165 6 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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