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TMS570LS3134PGE Datasheet(PDF) 8 Page - Texas Instruments |
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TMS570LS3134PGE Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 167 page  TMS570LS3134, TMS570LS2134, TMS570LS2124 SPNS165B – APRIL 2012 – REVISED MAY 2015 www.ti.com • Table 6-25: Added RAM power domain information in the table notes ...................................................... 83 • Table 6-26 (Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to "0xFF45FFFF" ....................................................................................................................... 84 • Table 6-38 (JTAG ID Code): Added JTAG Identification Code for Silicon Revision "Rev D" ........................... 107 • Table 7-7 (MibADC Recommended Operating Conditions): Updated/Changed Analog input clamp current from IAIC to IAIK ............................................................................................................................ 122 • Controller Area Network (DCAN) Section 7.5.1 (Features): Updated/Changed TRM references to the correct document titles .................................................................................................................... 134 • Section 7.9.1 Corrected size of SPI baud rate generator, 11 bit, not 5 bit ................................................ 140 • Table 7-22 (SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)): Updated/Changed table footnote to "... CLOCK PHASE bit (SPIFMTx.16) is cleared" ............................................................................................................................. 144 • Section 8 (Device and Documentation Support): Updated/Changed section to meet new requirements, including addition of several subsections .................................................................................................. 152 • Section 8.8 (Device Identification Code Register): Added Device ID code value for silicon Rev D .................... 155 • Section 8.9 (Die Identification Registers): Updated/Changed the address of the two die identification registers (DIEIDL and DIEIDH) to point to the original registers at location 0xFFFFFF7C and 0xFFFFFF80 for this section. 156 • Table 8-3 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rows ....................... 156 • Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section title ........................ 162 • Section 9.1 (Packaging Information): Updated/Changed the paragraph ................................................... 162 8 Revision History Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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