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TMS5702134DZWTQQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TMS5702134DZWTQQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 167 page  DMA POM DMM HTU1 HTU2 Switched Central Resource Main Cross Bar: Arbitration and Prioritization Control CRC Switched Central Resource Peripheral Central Resource Bridge Dual Cortex-R4F CPUs in Lockstep Switched Central Resource MibADC1 MibADC2 I2C N2HET1 GIO N2HET2 64KB Flash for EEPROM Emulation with ECC IOMM PMM VIM RTI DCC1 DCC2 3MB (B) Flash with ECC ETM-R4 RTP 64K (A) 64K 64K 64K 256KB RAM with ECC EMIF EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0] EMIF_ADDR[21:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE EMIF_nRAS EMIF_nCAS EMIF_nRW EMIF_nWAIT # 2 # 3 # 4 # 1 # 2 # 1 always on Core/RAM RAM Core # 5 # 3 Color Legend for Power Domains DCAN1 DCAN2 DCAN3 LIN SCI SPI4 MibSPI1 CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0] MIBSPI1_nCS[5:0] MIBSPI1_nENA SPI2 SPI2_CLK SPI2_SIMO SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MibSPI3 MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA MibSPI5 MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX SYS nPORRST nRST ECLK ESM nERROR MIBSPI5_CLK TMS570LS3134, TMS570LS2134, TMS570LS2124 www.ti.com SPNS165B – APRIL 2012 – REVISED MAY 2015 1.4 Functional Block Diagram A. For devices with 192KB RAM with ECC, the RAM #3 power domain is not supported. B. The TMS570LS2134 and TMS570LS2124 devices only support 2MB of Flash with ECC. Figure 1-1. Functional Block Diagram Copyright © 2012–2015, Texas Instruments Incorporated Device Overview 5 Submit Documentation Feedback |
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