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TMS5702134DPGEQQ1 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS5702134DPGEQQ1 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 167 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS570LS3134, TMS570LS2134, TMS570LS2124 SPNS165B – APRIL 2012 – REVISED MAY 2015 TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Microcontroller for Safety- • Multiple Communication Interfaces Critical Applications – Three CAN Controllers (DCANs) – Dual CPUs Running in Lockstep • 64 Mailboxes, Each With Parity Protection – ECC on Flash and RAM Interfaces • Compliant to CAN Protocol Version 2.0B – Built-In Self-Test (BIST) for CPU and On-chip – Standard Serial Communication Interface (SCI) RAMs – Local Interconnect Network (LIN) Interface – Error Signaling Module With Error Pin Controller – Voltage and Clock Monitoring • Compliant to LIN Protocol Version 2.1 • ARM® Cortex®-R4F 32-Bit RISC CPU • Can be Configured as a Second SCI – Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline – Inter-Integrated Circuit (I2C) – FPU With Single- and Double-Precision – Three Multibuffered Serial Peripheral Interfaces – 12-Region Memory Protection Unit (MPU) (MibSPIs) – Open Architecture With Third-Party Support • 128 Words With Parity Protection Each • Operating Conditions – Two Standard Serial Peripheral Interfaces (SPIs) – System Clock up to 180 MHz • Two Next Generation High-End Timer (N2HET) – Core Supply Voltage (VCC): 1.2 V Nominal Modules – I/O Supply Voltage (VCCIO): 3.3 V Nominal – N2HET1: 32 Programmable Channels – ADC Supply Voltage (VCCAD): 3.0 to 5.25 V – N2HET2: 18 Programmable Channels • Integrated Memory – 160-Word Instruction RAM Each With Parity – 3MB of Program Flash With ECC (LS3134) Protection – 2MB of Program Flash With ECC – Each N2HET Includes Hardware Angle (LS2134/2124) Generator – 256KB of RAM With ECC (LS3134/2134) – Dedicated High-End Transfer Unit (HTU) With – 192KB of RAM With ECC (LS2124) MPU for Each N2HET – 64KB of Flash With ECC for Emulated • Two 12-Bit Multibuffered ADC Modules EEPROM – ADC1: 24 Channels • 16-Bit External Memory Interface – ADC2: 16 Channels Shared With ADC1 • Common Platform Architecture – 64 Result Buffers With Parity Protection Each – Consistent Memory Map Across Family • General-Purpose Input/Output (GPIO) Pins – Real-Time Interrupt (RTI) Timer OS Timer Capable of Generating Interrupts – 96-Channel Vectored Interrupt Module (VIM) – 16 Pins on the ZWT Package – 2-Channel Cyclic Redundancy Checker (CRC) – 10 Pins on the PGE Package • Direct Memory Access (DMA) Controller • IEEE 1149.1 JTAG, Boundary Scan and ARM – 16 Channels and 32 Peripheral Requests CoreSight™ Components – Parity Protection for Control Packet RAM • JTAG Security Module – DMA Accesses Protected by Dedicated MPU • Packages • Frequency-Modulated Phase-Locked Loop – 144-Pin Quad Flatpack (PGE) [Green] (FMPLL) With Built-In Slip Detector – 337-Ball Grid Array (ZWT) [Green] • Separate Nonmodulating PLL • Trace and Calibration Capabilities – Embedded Trace Macrocell (ETM-R4) – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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