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TNETE2201BPJDRG4 Datasheet(PDF) 7 Page - Texas Instruments

Part # TNETE2201BPJDRG4
Description  1.25-GIGABIT ETHERNET TRANSCEIVER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETE2201BPJDRG4 Datasheet(HTML) 7 Page - Texas Instruments

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TNETE2201B
1.25GIGABIT ETHERNET TRANSCEIVER
SLLS367D − JUNE 1999 − REVISED AUGUST 2007
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
data reception (continued)
During a bus error condition or word alignment, the receive byte clocks RBC0 and RBC1 are stretched (never
truncated). When the incoming serial data does not meet its frequency requirements, then the receive byte clock
frequency is maintained at 62.5 MHz.
receive PLL operation
The receive PLL provides automatic locking to the incoming data. At power up, the maximum initial lock time
is 500
µs. The PLL can also be initiated or set to phase lock to the externally supplied reference clock by enabling
lock-to-reference (LCKREFN). The lock-to-reference causes the receive PLL to lock to 10
× the reference clock
(REFCLK) input providing a PLL preset and reset capability.
If during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data
and/or a frequency wander of up to 200 ppm, then the PLL recovers lock within 2.4
µs. Any condition exceeding
these values is considered a power-up scenario and the PLL recovers lock within 500
µs with a 0.1 µF capacitor
the PLL recovers lock within 10 ms on power up (see the following note).
NOTE:
A filter capacitor value of 0.1
µF can be used with the following consideration: The tracking
bandwidth of the PLL will be reduced due to the larger filter capacitor. This reduces the transmit and
receive PLL’s ability to reject low-frequency noise or wonder in the voltage supply or datastream.
Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50)
to reject power supply noise.
receiver word alignment
The TNETE2201B uses a 10-bit K28.5 character (comma character) word alignment scheme. The following
sections explain how this scheme works and how it realigns itself.
comma character on expected boundary
The TNETE2201B provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment
is enabled by forcing SYCNEN high. This enables the function that examines and compares ten bits of serial
input data to the K28.5 synchronization character. The K28.5 character is defined in the fibre channel standard
as a pattern consisting of 0011111010 (a negative number beginning disparity) with the 7 MSBs (0011111)
referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.
As long as the K28.5 character falls within the expected 10-bit word boundary, the received 10-bit data is
properly aligned and data realignment is not required. Figure 1 shows the timing characteristics of RBC0, RBC1,
SYNC and RD0 − RD9 while synchronized.
NOTE:
The
K28.5 character is valid on the rising edge of RBC1.
RBC0
RD0 − RD9
RBC1
SYNC
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
Figure 1. Synchronous Timing Characteristics Waveforms


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