TNETE2201B

1.25GIGABIT ETHERNET TRANSCEIVER

SLLS367D − JUNE 1999 − REVISED AUGUST 2007

5

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

I/O and DATA

DOUT_TXP

DOUT_TXN

62

61

Output

Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface

to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.25 Gbps.

DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is

low.

DIN_RXP

DIN_RXN

54

52

Input

Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface

from a copper or an optical I/F module. These terminals receive NRZ data at a rate of 1.25 Gbps and

are active when LOOPEN is held low.

LCKREFN

27

Input

Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied

REFCLK signal. LCKREFN prelocks or resets the receive PLL.

LOOPEN

19

Input

Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test

capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held

static during the loop-back test. LOOPEN is held low during standard operational state with external

serial outputs and inputs active.

RBC0

RBC1

31

30

Output

Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for synchronizing the

10-bit output data on RD0 − RD9. The 10-bit output data words are valid on the rising edges of RBC0

and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous

detect. The clocks are always expanded during data realignment and never slivered or truncated.

RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.

RC1,

RC0

49

48

Analog

Receive capacitor. RC0 and RC1 are external capacitor connections used for the receiver internal

PLL filter. The recommend value for this external capacitor is 2 nF (a value of 0.1

µF can also be used,

see Note 1).

RD0 − RD9

45,44,43,41

40,39,38,36

35,34

Output

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol

layer. The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the

K28.5 character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.

REFCLK

22

Input

Reference clock. REFCLK is an external 125 MHz input clock that synchronizes the receiver and

transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for

serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.

SYNC

47

Output

Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data

path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is

activated (asserted high). Note: SYNC is active on byte0 and, therefore, active on rising edge of

RCB1.

SYNCEN

24

Input

Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function

is activated. When this function is enabled, the transceiver detects the K28.5 character (0011111010

negative beginning disparity) in the serial data stream and realigns data on byte boundaries if

required. When SYNCEN is low, serial input data is unframed in RD0 − RD9.

TC1

TC0

16

17

Analog

Transmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal

PLL filter. The recommended value of this external capacitor is 2 nF (a value of 0.1

µF can also be

used, see Note 1).

TD0 − TD9

2,3,4,6

7,8,9,11

12,13

Input

Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver

for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising

edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

NOTE 1: A filter capacitor value of 0.1

µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due

to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage

supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power

supply noise.