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TPS22953DSQR Datasheet(PDF) 3 Page - Texas Instruments |
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TPS22953DSQR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 46 page GND (Exposed thermal pad) 1 2 3 4 Top View Bottom View IN IN BIAS EN 5 GND 10 9 8 7 OUT OUT SNS PG 6 CT GND (Exposed thermal pad) 1 2 3 4 IN IN BIAS EN 5 GND 10 9 8 7 OUT OUT SNS PG 6 CT TPS22954, TPS22953 www.ti.com SLVSCT5C – MARCH 2015 – REVISED JULY 2015 6 Device Comparison Table Device Quick Output Reverse Current Package (Pin) Body Size Pin Pitch Discharge Blocking DSQ (10) 2.00 mm x 2.00 mm 0.4 mm TPS22954 Yes No DQC (10) 2.00 mm x 3.00 mm 0.5 mm DSQ (10) 2.00 mm x 2.00 mm 0.4 mm TPS22953 No Yes DQC (10) 2.00 mm x 3.00 mm 0.5 mm 7 Pin Configuration and Functions Pin Functions PIN(1) I/O DESCRIPTION NAME NO. IN 1, 2 I Switch input. Bypass this input with a ceramic capacitor to GND. BIAS 3 I Bias pin and power supply to the device. Active high switch enable/disable input. Also acts as the input UVLO pin. Use external resistor divider to EN 4 I adjust the UVLO level. Do not leave floating. GND 5 – Device ground. VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device CT 6 O and limit the inrush current. CT Capacitor should be rated to 25V or higher. Power good. This pin is open drain which will pull low when the voltage on EN and/or SNS is below PG 7 O their respective VIL level. SNS 8 I Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating. OUT 9, 10 O Switch output. Thermal Pad – – Exposed thermal pad. Tie to GND. (1) Pinout applies to all package versions. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS22954 TPS22953 |
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