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TPL5111DDCT Datasheet(PDF) 3 Page - Texas Instruments |
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TPL5111DDCT Datasheet(HTML) 3 Page - Texas Instruments |
3 / 25 page TPL5111 VDD GND EN/ ONE_ SHOT DRVn DELAY/ M_DRV DONE 1 2 3 4 5 6 TPL5111 www.ti.com SNAS659A – JUNE 2015 – REVISED JULY 2015 5 Pin Configuration and Functions DDC Package 6-Lead SOT-23 Top View Pin Functions PIN TYPE(1) DESCRIPTION APPLICATION INFORMATION NO. NAME 1 VDD P Supply voltage 2 GND G Ground 3 DELAY/ I Time interval configuration (during Resistance between this pin and GND is used to M_DRV power on) and logic input for select the time interval. The manual Power ON signal manual Power ON (logic HIGH) can also connected to this pin. 4 DONE I Logic Input for watchdog Digital signal driven by the µC to indicate successful functionality processing. 5 DRVn O Power Gating output signal The ENABLE pin of the LDO or DC-DC converter is generated every tIP connected to this pin. DRVn is active HIGH. 6 EN/ I Select mode of operation When EN/ONE_SHOT = HIGH, the TPL5111 works ONE_SHOT as a TIMER. When EN/ONE_SHOT = LOW, the TPL5111 asserts DRVn one time for the programmed time interval. In this mode, the DRVn signal may be manually asserted by applying a logic HIGH to the DELAY/M_DRV pin. (1) G= Ground, P= Power, O= Output, I= Input. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPL5111 |
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