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BQ29312PW Datasheet(PDF) 4 Page - Texas Instruments |
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BQ29312PW Datasheet(HTML) 4 Page - Texas Instruments |
4 / 33 page bq29312 SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004 www.ti.com 4 ELECTRICAL CHARACTERISTICS TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 Supply current 1 No load at REG, TOUT, XALERT, SCLK, and SDATA. ZVCHG = off ,VMEN = on, 60 90 A ICC1 Supply current 1 and SDATA. ZVCHG = off ,VMEN = on, WDI no clock, Select VC5 = VC4 = 0 V TA = −25°C to 85°C 100 µA ICC2 Supply current 2 (Depends of VM topology selected) No load at REG, TOUT, XALERT, SCLK, and SDATA. ZVCHG = off, VMEN = off, WDI no clock TA = −25°C to 85°C 25 50 µA I(SLEEP) Sleep current No load at REG, TOUT, XALERT, SCLK, and SDATA. CHG, DSG and ZVCHG = off, REG = on, VMEN = off, WDI no clock, SLEEP = REG or OPEN TA = −25°C to 85°C 20 40 µA I(SHIP) Ship current REG, CHG, DSG and ZVCHG = off, REG = off, VMEN = off, WDI no clock, VPACK= 0 V TA = −25°C to 85°C 0.1 1.0 µA 3.3 V LDO 8.0 V< BAT or PACK ≤ 25 V, IOUT ≤ 25 mA −4% 3.3 2% V 6.5 V< BAT or PACK ≤ 8 V, IOUT ≤ 25 mA −9% 3.3 2% V V(REG) Regulator output voltage 5.4 V ≤ BAT or PACK ≤ 6.5 V, IO ≤ 16 mA TA =− 25°C to 85°C −9% 3.3 2% V voltage 4.5 V ≤ BAT or PACK ≤ 25 V, IO ≤ 2 mA −2% 3.3 2% V ∆V(EGTEMP) Regulator output change with temperature 5.4 V ≤ BAT ≤ 25 V, IO = 2 mA, TA =− 25°C to 85°C ±0.2% ∆V(REGLINE) Line regulation 5.4 V ≤ BAT or PACK ≤ 25 V, IO = 2 mA 3 10 mV ∆V(REGLOAD) Load regulation BAT = 14 V, 0.2 mA ≤ IO ≤ 2 mA 7 15 mV ∆V(REGLOAD) Load regulation BAT = 14 V, 0.2 mA ≤ IO ≤ 25 mA 40 100 mV IMAX Current limit BAT = 14 V, REG = 3.0 V 25 100 mA IMAX Current limit BAT = 14 V, REG = 0 V 12 50 mA CELL VOLTAGE MONITOR V(CELL OUT) CELL output V(Cn) – V(Cn + 1) = 0 V, 8.0 V ≤ BAT or PACK ≤ 25 V 0.975 V V(CELL OUT) CELL output V(Cn) – V(Cn + 1) = 4.5 V, 8.0 V ≤ BAT or PACK ≤ 25 V 0.3 V REF CELL output Mode(1), 8.0 V ≤ BAT or PACK ≤ 25 V −1% 0.975 1% V PACK CELL output Mode(2) −5% PACK /25 5% V K CELL scale factor K = {CELL output (VC5 = 0.0 V, VC4 = 4.5 V) −CELL output (VC5 = VC4 = 0.0 V)/ 4.5 0.147 0.150 0.153 K CELL scale factor K = {CELL output (VC2 = 13.5 V, VC1 = 18.0 V) −CELL output (VC2 = VC1 = 13.5 V)/ 4.5 0.147 0.150 0.153 VICR CELL output offset error CELL output (VC2 = 17.0 V, VC1 = 17.0 V) CELL output (VC2 = VC1 = 0.0 V) −1 mV R(BAL) Cell balance internal resistance rds(ON) for internal FET switch at VDS = 2.0 V 200 400 800 Ω (1) Register Address =0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03,b0(VMEN) = 1 (2) Register Address = 0x03, b1(PACKOUT) = 1, b0( VMEN) = 1 |
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