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TPS2111APWR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS2111APWR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 26 page D0 D1 VSNS ILIM IN1 OUT IN2 GND 1 2 3 4 8 7 6 5 TPS2110A TPS2111A www.ti.com SBVS043A – MARCH 2004 – REVISED MARCH 2010 DEVICE INFORMATION TRUTH TABLE D1 D0 VI(VSNS) > 0.8 V (1) VI(IN2) > VI(IN1) OUT(2) 0 0 X X IN2 0 1 Yes X IN1 0 1 No No IN1 0 1 No Yes IN2 1 0 X X IN1 1 1 X X Hi-Z (1) X = Don’t care. (2) The undervoltage lockout circuit causes the output to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. PIN CONFIGURATIONS PW PACKAGE TSSOP-8 (TOP VIEW) Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION D0 1 I TTL- and CMOS-compatible input pins. Each pin has a 1-mA pull-up. The Truth Table illustrates the functionality of D0 and D1. D1 2 I GND 5 Power Ground Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above IN1 8 I the UVLO threshold and at least one supply exceeds the internal VDD UVLO. Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is IN2 6 I above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. A resistor (RILIM) from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the ILIM 4 I TPS2110A and TPS2111A, respectively. OUT 7 O Power switch output In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if VSNS 3 I the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The Truth Table illustrates the functionality of VSNS. Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TPS2110A TPS2111A |
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