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TPS2206ADBR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS2206ADBR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 34 page TPS2204A TPS2206A TPS2210A SLVS449A − DECEMBER 2002 − REVISED MAY 2003 www.ti.com 4 ELECTRICAL CHARACTERISTICS Continued TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Normal II(3.3V) VO(xVCC) = VO(xVPP) = 3.3 V and 140 200 Normal operation II(5V) VO(xVCC) = VO(xVPP) = 3.3 V and also for RESET = 0 V 8 12 II Input current, operation II(12V) also for RESET = 0 V 100 180 A II Input current, quiescent Shutdown II(3.3V) 0.3 2 µA quiescent Shutdown mode II(5V) VO(xVCC) = VO(xVPP) = Hi-Z 0.1 2 mode II(12V) VO(xVCC) = VO(xVPP) = Hi-Z 0.3 2 VO(xVCC) = 5 V, 10 Ilkg Leakage current, Shutdown mode VO(xVCC) = 5 V, VI(5V) = VI(12V) = 0 V TJ = 100°C 50 A Ilkg Leakage current, output off state Shutdown mode VO(xVPP) = 12 V, 10 µA output off state VO(xVPP) = 12 V, VI(5V) = VI(12V) = 0 V TJ = 100°C 50 LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT II(RESET)(1) RESET = 5.5 V −1 1 II(RESET)(1) RESET = 0 V −30 −20 −10 II(SHDN)(1) SHDN = 5.5 V −1 1 II Input current, logic II(SHDN)(1) SHDN = 0 V −50 −3 µA II Input current, logic II(LATCH)(1) LATCH = 5.5 V 50 µA II(LATCH)(1) LATCH = 0 V −1 1 II(CLOCK, DATA) 0 V to 5.5 V −1 1 VIH High-level input voltage, logic 2 V VIL Low-level input voltage, logic 0.8 V VO(sat) Output saturation voltage at OC IO = 2 mA 0.14 0.4 V Ilkg Leakage current at OC VO(/OC) = 5.5 V 0 1 µA (1) LATCH has low current pulldown. RESET and SHDN have low-current pullup. UVLO AND POR (POWER-ON RESET) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI(3.3V) Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V Vhys(3.3V) UVLO hysteresis voltage at VA (1) 100 mV VI(5V) Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 2.9 V Vhys(5V) UVLO hysteresis voltage at 5 V(1) 100 mV tdf Delay time for falling response, UVLO(1) Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) 4 µs VI(POR) Input voltage, power-on reset(1) 3.3-V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. 1.7 V (1) Specified by design; not tested in production. |
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