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TPS3618-50DGKT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3618-50DGKT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 17 page  www.ti.com VIT VBAT VDD VOUT RESET td t t t td TPS3617 TPS3618 SLVS339D – DECEMBER 2000 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) 1.65 V ≤ V DD≤ 5.5 V, RLRESET = 1 MΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to +85°C), unless otherwise noted. Typical values are at T J = +25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ci Input capacitance, any input VI = 0 V to 5 V 5 pF VDD VIH = VIT + 0.2 V, VIL = VIT– 0.2 V 6 µs tw Pulse Width VDD > VIT + 0.2 V, VIL = 0.3 x VDD, WDI 100 ns VIH = 0.7 x VDD td VDD ≥ VIT + 0.2 V, Delay time 60 100 140 ms See timing diagram t(tout) VDD > VIT + 0.2 V, Watchdog time-out 0.48 0.8 1.12 s See timing diagram VIL = VIT– 0.2 V, VDD to RESET 2 5 VIH = VIT + 0.2 V Propagation (delay) time, tPHL µs high-to-low-level output VIL = VPFI– 0.2 V, PFI to PFO 3 5 VIH = VPFI + 0.2 V Transition time VDD to VBAT 3 µs TIMING DIAGRAM Table 1. FUNCTION TABLE VDD > VIT VDD > VBAT VOUT RESET 0 0 VBAT 0 0 1 VDD 0 1 0 VDD 1 1 1 VDD 1 4 Submit Documentation Feedback |
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