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TPS40074 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS40074 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 38 page www.ti.com ELECTRICAL CHARACTERISTICS TPS40074 SLUS617B – APRIL 2005 – REVISED OCTOBER 2006 T A = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range, VIN 4.5 28 V OPERATING CURRENT IDD Quiescent current Output drivers not switching 2.5 3.5 mA LVBP VLVBP Output voltage TA = TJ = 25°C 3.9 4.2 4.5 V OSCILLATOR/RAMP GENERATOR fOSC Accuracy 450 500 550 kHz VRT RT voltage 2.23 2.40 2.58 V tON(min) Minimum output pulse time(1) CHDRV = 0 nF 150 ns VIH High-level input voltage, SYNC 2 5 V VIL Low-level input voltage, SYNC 0.8 ISYNC Input current, SYNC 5 10 µA VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz 84% 95% Maximum duty cycle VFB = 0 V, fSW = 1 MHz 76% 93% VKFF Feed-forward voltage 0.35 0.40 0.45 V IKFF Feed-forward current operating range(1) 20 1100 µA SOFT START ISS Charge current 7 12 17 µA tDSCH Discharge time CSS = 3.9 nF 25 75 µs CSS = 3.9 nF, VSS rising from 0.7 V to 1.6 tSS Soft-start time 210 290 500 V Command zero output voltage(2)(1) 300 mV DBP VDD > 10 V 7 8 9 VDBP Output voltage V VVDD = 4.5 V, IOUT = 25 mA 4.0 4.3 ERROR AMPLIFIER TA = TJ = 25°C 0.698 0.700 0.704 VFB Feedback regulation voltage total variation 0°C ≤ T A = TJ ≤ 85°C 0.690 0.700 0.707 V -40°C ≤ T A = TJ ≤ 85°C 0.690 0.700 0.715 VSS(offset) Soft-start offset from VSS(1) Offset from VSS to error amplifier 1 GBWP Gain bandwidth(1) 5 10 MHz AVOL Open loop gain 50 dB ISRC Output source current 2.5 4.5 mA ISINK Output sink current 2.5 6 IBIAS Input bias current VFB = 0.7 V –250 0 nA SHORT CIRCUIT CURRENT PROTECTION IILIM Current sink into ILIM pin 115 135 150 µA VILIM(ofst) Current limit offset voltage VILIM = 11.5 V, (VSW - VILIM) VVDD = 12 V –50 –30 –10 mV tHSC Minimum HDRV pulse width During short circuit 135 225 ns Propagation delay to output(1) 50 ns tBLANK Blanking time(1) 50 ns tOFF Off time during a fault (SS cycle times) 7 cycles (1) Ensured by design. Not production tested. (2) For zero output voltage only. Does not assure lack of activity on HDRV or LDRV. 4 Submit Documentation Feedback |
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