(

)

(

)

f

A

A

SW

8 3.48

C

R

7.9

-

=

´

´

(

)

(

)

(

)

KFF

A

IN min

R

8 3.48

R

495k

499k

0.1

V

3.48

´

-

=

=

W =

W

´

-

UDG-02132

Clock

PWM RAMP

PowerGood

VIN

UVLO Threshold

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2

TPS40054, TPS40055, TPS40057

SLUS593I – DECEMBER 2003 – REVISED DECEMBER 2014

www.ti.com

Feature Description (continued)

Figure 7. Undervoltage Lockout Operation

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal startup voltage, the maximum duty cycle is reduced approximately 10% at the

nominal startup voltage.

The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter

starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents

select the startup voltage, the approximate amount of hysteresis voltage is shown in Figure 3.

Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This

applies to applications which have high impedance on the input voltage line or which have excessive ringing on

shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and cause a

UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to prevent the

nuisance UVLO shutdown.

(3)

0.1 V (from 8 V to 7.9 V).

(4)

diode can be a small-signal switching diode or Schottky rated for more then 20 V. Figure 8 shows a typical

implementation using a small switching diode.

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal startup voltage, the maximum duty cycle is reduced approximately 10% at the

nominal startup voltage.

10

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