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TPS53647RTAR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS53647RTAR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 120 page ( ) O ISUM M isum ISUM REF I 5m g R V V n ´ W ´ ´ = + 4 TPS53647 SLUSC39A – JUNE 2015 – REVISED JULY 2016 www.ti.com Product Folder Links: TPS53647 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NAME NO. ISUM 12 O A resistor (RISUM) connected between this pin and VREF pin determines the droop. (where n is the number of phases) NC 7 — No connection. Leave the pin open or pull up to V3R3 pin. 8 33 — No connection. 34 OCL-R 1 I A resistor (ROCL-R) connected between this pin and GND and the voltage level (VOCL-R)select 1 of 16 OCP levels (per phase current-limit). VOCL-R also sets 1 of 4 RAMP levels. The device latches these settings when V3R3 powers up. O-USR 30 I Voltage divider to VREF pin. A resistor (RO-USR) connected between this pin and GND selects 1 of 7 OSR thresholds or OFF. The voltage level (VO-USR) )sets 1 of 7 USR levels or OFF. The device latches these settings when V3R3 powers up. PMB_ALERT 25 O I2C PMBus interrupt line. Open drain. 3.3-V and 1.8-V logic level. PMB_CLK 24 I I2C PMBus clock. 3.3-V and 1.8-V logic level. PMB_DIO 26 I/O I2C PMBus digital I/O line. 3.3-V and 1.8-V logic level. PWM1 38 O PWM signals for each phase PWM2 37 PWM3 36 PWM4 35 RESET 21 I Reset pin. If this pin is low for more than 1000 ns, the controller pulls the output voltage to the VBOOT level. SKIP-NVM 39 O A resistor (R SKIP-NVM) connected between this pin and GND sets either pinstrap or NVM configuration mode. This pin can also connect to the FCCM pin of TI smart power stages (ex: CSD95372BQ5MC) for SKIP or FCCM operation. SLEW-MODE 29 I Voltage divider to VREF pin. A resistor (RSLEW-MODE) connected between this pin and GND sets 8 slew rates. The voltage level (VSLEW-MODE) sets 4-bit operation modes. Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5). Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase interleaving; 0 for 4 phase interleaving individually). Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable). Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The device latches these settings when V3R3 powers up. TSEN 40 I Connect to the TAO/FAULT pin of TI smart power stages (ex: CSD95372BQ5MC) to sense the highest temperature of the power stages and to sense the fault signal from the power stages. V3R3 14 O 3.3-V LDO output. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. V5 15 P 5-V power input. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. This pin is used to power all internal analog circuits. VBOOT 31 I Voltage divider to VREF pin. A resistor (RVBOOT) connected between this pin and GND sets 3 bits (B[3:1]). The voltage level (VVBOOT) sets 4 bits (B[7:4]). The total 7 bits set 7 of 8 bits of VID of boot voltage (B[7:1]). The device latches these settings when V3R3 powers up. VIN 16 P Input voltage supply. This pin is also used for input voltage sensing for on-time control and input undervoltage lockout (UVLO). VR_RDY 18 O Power good open-drain output for the controller. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. VR_FAULT 27 O VR fault indicator (open-drain). The failures include shorts of the high-side FETs, over temperature, output overvoltage, and overcurrent conditions of the input. The fault signal should be used on the platform to remove the power source either by firing a shunting SCR to blow a fuse or by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is LOW. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. VR_HOT 19 O Thermal flag open drain output. Active low. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. VREF 13 O 1.7-V, 500-µA, LDO reference voltage. Bypass this pin to GND with a ceramic capacitor with a value of 0.33 µF. Connect the VREF pin to the REFIN pin of TI smart power stages (ex: CSD95372BQ5MC) as the current-sense reference voltage. |
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