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TPS54310PWP Datasheet(PDF) 3 Page - Texas Instruments |
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TPS54310PWP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH RT SYNC SS/ENA VBIAS VIN VIN VIN PGND PGND PGND TPS54310 www.ti.com SLVS412E – DECEMBER 2001 – REVISED DECEMBER 2014 5 Device Comparison Table DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE TPS54311 0.9 V TPS54314 1.8 V TPS54372 DDR/Adjustable TPS54312 1.2 V TPS54315 2.5 V TPS54373 Prebias/Adjustable TPS54313 1.5 V TPS54316 3.3 V TPS54380 Sequencing/Adjustable 6 Pin Configuration and Functions PWP PACKAGE 20-PINs Top View Pin Functions PIN DESCRIPTION NAME NO. Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor AGND 1 and SYNC pin. Make PowerPAD connection to AGND. Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the BOOT 5 high-side FET driver. COMP 3 Error amplifier output. Connect compensation network from COMP to VSENSE. Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper PGND 11–13 areas to the input and output supply returns, and negative terminals of the input and output capacitors. PH 6–10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor. Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low PWRGD 4 when SS/ENA is low or internal shutdown signal active. RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and SS/ENA 18 capacitor input to externally set the start-up time. Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin SYNC 19 select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a VBIAS 17 high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor. Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to VIN 14–16 device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS54310 |
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