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TPS54310 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS54310 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 28 page TPS54310 SLVS412E – DECEMBER 2001 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN, SS/ENA, SYNC –0.3 7 V RT –0.3 6 V VI Input voltage VSENSE –0.3 4 V BOOT –0.3 17 V VBIAS, PWRGD, COMP –0.3 7 V VO Output voltage PH –0.6 10 V PH Internally Limited IO Output voltage COMP, VBIAS 6 mA PH 6 A Sink current COMP 6 mA SS/ENA, PWRGD 10 mA Voltage differential AGND to PGND –0.3 0.3 V Continuous power dissipation See Dissipation Ratings TJ Operating virtual junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22- ±1500 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN MAX UNIT VI Input voltage range 3 6 V TJ Operating junction temperature –40 125 °C 7.4 Thermal Information (1) TPS54310 THERMAL METRIC(2) PWP UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 26 °C/W RθJA Junction-to-ambient thermal resistance (without solder coverage on PowerPad) 57.5 (1) Test board conditions: (a) 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch (b) 1.5 oz copper traces located on the top of the PCB (c) 1.5 oz copper ground plane on the bottom of the PCB (d) Ten thermal vias (see recommended land pattern in application section of this data sheet) (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 4 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: TPS54310 |
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