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Electrical Characteristics

TPS54311-EP, TPS54312-EP,

TPS54313-EP, TPS54314-EP,

TPS54315-EP, TPS54316-EP

SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE, VIN

Input voltage range

3

6

V

FSEL

≤ 0.8 V,

6.2

9.6

RT open

xxx

Quiescent current

FSEL

≥ 2.5 V,

mA

8.4

12.8

Phase pin open,

RT open

Shutdown,

SS/ENA = 0 V

1

1.4

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

2.95

3

V

Stop threshold voltage, UVLO

2.7

2.8

Hysteresis voltage, UVLO

0.14

V

Rising and falling edge deglitch,

2.5

µs

BIAS VOLTAGE

Output voltage, VBIAS

2.7

2.8

2.95

V

100

µA

OUTPUT VOLTAGE

0.9

V

TPS54311

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

1.2

V

TPS54312

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

1.5

V

TPS54313

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

1.8

V

TPS54314

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

2.5

V

TPS54315

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

3.3

V

TPS54316

3

≤ V

0

≤ I

–55

°C ≤ T

–3.0%

3.0%

REGULATION

350

≤ f

0.21

%/V

350

≤ f

0.21

%/A

OSCILLATOR

FSEL

≤ 0.8 V,

RT open

255

350

450

Internally set free-running frequency

kHz

range

FSEL

≥ 2.5 V,

RT open

400

550

700

RT = 180 k

252

280

308

Externally set free-running frequency

RT = 160 k

Ω (1% resistor to AGND)

290

312

350

kHz

range

RT = 68 k

663

700

762

High-level threshold voltage at FSEL

2.5

V

Low-level threshold voltage at FSEL

0.8

V

50

ns

330

700

kHz

0.75

V

(1)

Specified by design

(2)

Static resistive loads only

(3)

Specified by the circuit used in Figure 10.

(4)

To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R

≤ 1 kΩ and C

≤ 68 pF.

5

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