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TPS54900PW Datasheet(PDF) 6 Page - Texas Instruments |
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TPS54900PW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 17 page TPS54900 SLVS405 − OCTOBER 2001 6 www.ti.com detailed description (continued) enable (EN) If the EN pin is held low when the TPS54900 is powered up, the oscillator starts and free-runs. Serial commands to initialize the PWM clocks and program the output levels are accepted, but the outputs are held off and do not begin regulating until the EN pin is pulled above VIH. If the TPS54900 is first programmed with outputs enabled and then EN is pulled LOW, all outputs are shut off and all DACs are reset. The EN pin does not affect the oscillator, which continues to run and maintain PWM phase stagger. The previously programmed channel voltages are also maintained in the registers. If EN is pulled above VIH, the TPS54900 channels start up through the soft-start sequence and reach regulation at the previously programmed target voltages. Bypass mode may be forced on all outputs by pulling EN above VIN – 0.5 V. When bypass mode is forced, all four channels step up to VIN in 200-mV increments. over current protection During steady state operation, the overcurrent protection threshold is 250 mA minimum, 750 mA maximum, sampled approximately 500 ns after the start of the switching cycle. When overcurrent is sensed in the PMOSFET, the output is disabled for a hiccup time of 170 ms to 360 ms (SCLK = 4.416 MHz). In the pass-through mode, the overcurrent detection remains active and the hiccup behavior is unchanged. thermal shutdown Thermal shutdown disables the controller if the junction temperature exceeds 150 °C. The hysteresis is 10°C. This shuts down off the switching circuitry and resets the soft-start circuitry. If the IC returns to normal temperature, it restarts and returns to the programmed target voltages. serial control interface timing diagram 0 1 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 S1 D0 D1 D2 D3 D4 D5 D6 D7 S0 SDO (Read: R/W = 1) SDO (Write: R/W = 0) SDI SCLK SFS ADR 1 High−Z S2 10 R/W ADR 2 15 14 ADR 0 S3 12 13 11 High−Z High−Z High−Z |
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