 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT71T75802S100BGI Datasheet(PDF) 1 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT71T75802S100BGI Datasheet(HTML) 1 Page - Integrated Device Technology |
|
|
1 / 25 page  APRIL 2004 DSC-5313/08 1 ©2004 Integrated Device Technology, Inc. A0-A19 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/ W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/ LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input N/A TDI Test Data Input Input N/A TCK Test Clock Input N/A TDO Test Data Input Output N/A TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5313 tbl 01 Pin Description Summary Features x x x x x 512K x 36, 1M x 18 memory configurations x x x x x Supports high performance system speed - 225 MHz (3.0 ns Clock-to-Data Access) x x x x x ZBTTM Feature - No dead cycles between write and read cycles x x x x x Internally synchronized output buffer enable eliminates the need to control OE OE OE OE OE x x x x x Single R/ W W W W W (READ/WRITE) control pin x x x x x Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications x x x x x 4-word burst capability (interleaved or linear) x x x x x Individual byte write ( BW BW BW BW BW1 - BW BW BW BW BW4) control (May tie active) x x x x x Three chip enables for simple depth expansion x x x x x 2.5V power supply (±5%) x x x x x 2.5V I/O Supply (VDDQ) x x x x x Power down controlled by ZZ input x x x x x Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) x x x x x Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) IDT71T75602 IDT71T75802 512K x 36, 1M x 18 2.5V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Description The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Megabit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71T75602/802 contain data I/O, address and control signal registers.Outputenableistheonlyasynchronoussignalandcanbeused to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71T75602/802 tobesuspendedaslongasnecessary.Allsynchronousinputsareignored when( CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious values. There are three chip enable pins ( CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not assertedwhenADV/ LDislow,nonewmemoryoperationcanbeinitiated. |
Similar Part No. - IDT71T75802S100BGI |
|
Similar Description - IDT71T75802S100BGI |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
