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TPS62134DRGTT Datasheet(PDF) 3 Page - Texas Instruments

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Part # TPS62134DRGTT
Description  TPS62134x, 17-V Input, Step-down Converter With Low-Power Mode Input for Intel Skylake Platform
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS62134DRGTT Datasheet(HTML) 3 Page - Texas Instruments

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background image
FBS
8
7
6
5
13
14
15
16
1
2
3
4
12
11
10
9
Exposed
Thermal PAD
AGND
SS
VID1
PGND
PGND
LPM
EN
TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com
SLVSC20D – JANUARY 2015 – REVISED MAY 2015
6 Device Comparison Table
PART NUMBER
PACKAGE MARKING
OUTPUT VOLTAGE
TPS62134A
134A
TPS62134B
134B
See Table 1
TPS62134C
134C
TPS62134D
134D
7 Pin Configuration and Functions
RGT Package
16-Pin VQFN With Thermal Pad
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Output voltage sense pin and connection for the control loop circuitry. The VOS pin must be connected
1
VOS
I
directly at the output capacitor.
2
This pin is a switch node and is connected to the internal MOSFET switches. Connect an inductor
SW
PWR
between the SW pin and output capacitor.
3
Output power-good pin. The PG pin is an open drain and requires a pullup resistor. If this pin is not in use,
4
PG
O
leave it floating.
Output-voltage feedback pin. This pin is used for a positive remote sense of the load voltage. The FBS pin
5
FBS
I
must be connected close to the load-supply node on the output bus.
Analog ground pin. The AGND pin must be connected directly to the exposed thermal pad and common
6
AGND
ground plane.
7
SS
O
Soft-start pin. An external capacitor connected to this pin sets the soft-start time.
8
VID1
I
Output-voltage selection pins (VIDx).
9
VID0
Supply-voltage pin for the internal control circuitry. Connect the AVIN pin to the same source as the PVIN
10
AVIN
I
pin.
11
PVIN
PWR
Supply-voltage pins for the internal power stage.
12
13
EN
I
Enable and disable input pin. An internal pulldown resistor maintains logic-level low if the pin is floating.
14
LPM
I
Low-power-mode input pin.
15
Power ground. The PGND pin must be connected directly to the exposed thermal pad and common
PGND
ground plane.
16
Exposed
The exposed thermal pad must be connected to the AGND (6) pin, PGND (15 and 16) pins, and common
Thermal
ground plane. The thermal pad must be soldered to achieve appropriate power dissipation and
Pad
mechanical reliability.
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D


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