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NCP1216AD133R2G Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP1216AD133R2G Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 18 page  NCP1216, NCP1216A www.onsemi.com 10 Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with a bunch of simple logical equations: POWER−ON: If VCC < VCCOFF then the Current Source is ON, no output pulses If VCC decreasing > VCCON then the Current Source is OFF, output is pulsing If VCC increasing < VCCOFF then the Current Source is ON, output is pulsing Typical values are: VCCOFF = 12.2 V, VCCON = 10 V To better understand the operational principle, Figure 18 offers the necessary light: 10 30 50 70 90 Figure 18. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor VCCOFF = 12.2 V VCCON = 10 V Vripple = 2.2 V ON, I = 8 mA OFF, I = 0 mA Output Pulse The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge Qg. If we select a 600 V 10 A MOSFET featuring a 30 nC Qg, then we can compute the resulting average consumption supported by the DSS which is: Itotal [ Fsw Qg ) ICC1. (eq. 1) The total IC heat dissipation incurred by the DSS only is given by: Itotal Vpin8. (eq. 2) Suppose that we select the NCP1216P065 with the above MOSFET, the total current is (30 n 65 k) ) 900 m + 2.9 mA. (eq. 3) Supplied from a 350 VDC rail (250 VAC), the heat dissipated by the circuit would then be: 350 V 2.9 mA + 1W (eq. 4) As you can see, it exists a tradeoff where the dissipation capability of the NCP1216 fixes the maximum Qg that the circuit can drive, keeping its dissipation below a given target. Please see the “Power Dissipation” section for a complete design example and discover how a resistor can help to heal the NCP1216 heat equation. Application note AND8069/D details tricks to widen the NCP1216 driving implementation, in particular for large Qg MOSFETs. This document can be downloaded at www.onsemi.com/pub/Collateral/AND8069−D.PDF. Ramp Compensation Ramp compensation is a known mean to cure sub−harmonic oscillations. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50% and 100% of the inductor down−slope. Figure 19 depicts how internally the ramp is generated: CS L.E.B 19 k 2.9V 0V Figure 19. Inserting a Resistor in Series with the Current Sense Information brings Ramp Compensation From Set−point Rsense Rcomp DCmax = 75°C In the NCP1216, the ramp features a swing of 2.9 V with a Duty cycle max at 75%. Over a 65 kHz frequency, it corresponds to a 2.9 0.75 65 kHz + 251 mV ms ramp. (eq. 5) In our FLYBACK design, let’s suppose that our primary inductance Lp is 350 mH, delivering 12 V with a Np : Ns ratio of 1:0.1. The OFF time primary current slope is thus given by: Vout ) Vf Lp Np Ns + 371 mA msor37 mV ms (eq. 6) when projected over an Rsense of 0.1 W, for instance. If we select 75% of the down−slope as the required amount of ramp compensation, then we shall inject 27 mV/ ms. Our internal compensation being of 251 mV/ ms, the divider ratio (divratio) between Rcomp and the 19 kW is 0.107. A few lines of algebra to determine Rcomp: 19 k divratio 1 * divratio + 2.37 kW (eq. 7) Frequency Jittering Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. NCP1216 offers a $4% deviation of |
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