NCP12510BSN100T1G datasheet(22/27 Pages) ONSEMI

Part #	NCP12510BSN100T1G

Description	Current-Mode PWM Controller for Off-line Power Supplies

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP12510

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The armed flag is generated with first DRV pulse, but only

if the first DRV pulse is synchronized with VCC(on) event. If

the FB pin is forced to ground during the VCC(on) event and

it is released afterwards, the armed flag is not generated. The

Figure 54 shows the cases of grounded FB pin at the

beginning of start−up sequence.

If the armed flag isn’t active and UVLO comes, the

controller newly starts after double−hiccup auto−recovery

sequence. Then, if UVLO comes again, the controller is

latched off. DRV pulses are authorized during the whole first

VCC going−down cycle. If any DRV pulse doesn’t come

during this time, the double−hiccup auto−recovery sequence

is coming.

The armed flag could be canceled by two conditions.

When the controller gets into regulation after start−up

sequence, i.e. during the eight consecutive switching cycles

is current setpoint voltage under Vlimit, the armed flag is

called off – this is the first armed flag cancelation condition.

When the start−up sequence isn’t complete and is

interrupted by grounded FB pin, the armed flag is called off

– this is the second armed flag cancelation condition. The

Figure 55 shows the cases of interrupted start−up sequence

by grounded FB pin.

If the start−up sequence is interrupted by grounded FB

pin, the armed flag is canceled. Then, if UVLO comes, the

controller newly starts after double−hiccup auto−recovery

sequence. Then, if UVLO comes again, the controller is

latched off.

The Figure 56 shows the case of operation, when the

controller can operate under some master system with

superordinate function. Then, the FB pin is used for

authorization or denial DRV pulses. If the normal operation

state is interrupted for a long time and afterwards the

soft−start is demanded for proper start−up of power supply,

the VCC have to be pulled−down below VCC(reset) level.

Then, if the FB isn’t grounded, the new start−up sequence

are initialized when VCC touches VCC(on) level + 200

ms

safety period. During this new start−up sequence is

generated the armed flag.

t

VCC (t)

VDRV (t)

VCC(on)

VCC(min)

VCC(reset)

t

flag

VCS (t)

Vlimit

0

t

VFB (t)

1

8 cycles

new sequence

FB@

gnd

8 cycles

FB@

gnd

Stop DRV pulses by

Master Sytem

Supply voltage VCC is

controlled by Master System

FB@

gnd

The IC must be reset to

ensure the soft -start

after release the FB

8 cycles

1

Grounded FB @VCC(on)

→ No Armed flag

Figure 56. The Master system driving the controller by forcing the FB pin to ground.

Armed

Slope Compensation

The NCP12510 includes an internal slope compensation

signal. This is the buffered oscillator clock delivered during

the on−time only. Its amplitude is around 2.5 V at the

maximum duty ratio. Slope compensation is a known means

used to cure sub harmonic oscillations in CCM−operated

current−mode converters. These oscillations take place at

half the switching frequency and occur only during

Continuous Conduction Mode (CCM) with a duty ratio

greater than 50%. To lower the current loop gain, one usually

injects between 50 and 100% of the primary inductance

downslope. Figure 57 depicts how the ramp is generated

internally. Please note that the ramp signal will be

disconnected from the CS pin during the off−time.

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NCP12510BSN100T1G Datasheet(PDF) 22 Page - ON Semiconductor

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