NCP1587, NCP1587A

http://onsemi.com

7

UVLO

Undervoltage Lockout (UVLO) is provided to ensure that

support the internal rails and power the converter. For the

NCP1587/A, the UVLO is set to permit operation when

converting from a 5.0 input voltage.

Overcurrent Threshold Setting

NCP1587/A can easily program an Overcurrent

Threshold ranging from 50 mV to 550 mV, simply by adding

a resistor (RSET) between BG and GND. During a short

an internal 10

drop will be sampled and internally held by the device as

Overcurrent Threshold. The OC setting procedure overall

between BG and GND, the programmed threshold will be:

IOCth +

IOCSET @ ROCSET

RDS(on)

(eq. 1)

RSET values range from 5 k

is not connected, the device switches the OCP threshold to

a fixed 375 mV value: an internal safety clamp on BG is

triggered as soon as BG voltage reaches 700 mV, enabling

the 375 mV fixed threshold and ending OC setting phase.

The current trip threshold tolerance is

±25 mV. The accuracy

of the set point is best at the highest set point (550 mV). The

accuracy will decrease as the set point decreases.

Current Limit Protection

In case of a short circuit or overload, the low−side (LS)

FET will conduct large currents. The controller will shut

down the regulator in this situation for protection against

the end of each of the LS−FET turn−on duration to sense the

over current trip point. While the LS driver is on, the Phase

voltage is compared to the internally generated OCP trip

voltage. If the phase voltage is lower than OCP trip voltage,

an overcurrent condition occurs and a counter is initiated.

When the counter completes, the PWM logic and both

HS−FET and LS−FET are turned off. The controller has to

go through a Power On Reset (POR) cycle to reset the OCP

fault.

Drivers

The NCP1587 and NCP1587A include gate drivers to

switch external N−channel MOSFETs. This allows the

devices to address high−power as well as low−power

conversion requirements. The gate drivers also include

adaptive non−overlap circuitry. The non−overlap circuitry

increase efficiency, which minimizes power dissipation, by

minimizing the body diode conduction time.

A detailed block diagram of the non−overlap and gate

drive circuitry used in the chip is shown in Figure 9.

Figure 9. Block Diagram

BST

TG

PHASE

BG

GND

FAULT

FAULT

8

2

1

4

3

2 V

-

+

-

+

Careful selection and layout of external components is

required, to realize the full benefit of the onboard drivers.

and SWN must be placed as close as possible to the IC. The

current paths for the TG and BG connections must be

optimized. A ground plane should be placed on the closest

layer for return currents to GND in order to reduce loop area

and inductance in the gate drive circuit.