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BQ29311PWR Datasheet(PDF) 5 Page - Texas Instruments |
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BQ29311PWR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page bq29311 SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003 www.ti.com 5 ELECTRICAL CHARACTERISTICS CONTINUED TA = 25°C, CREG = 1 µF, VCC = 14 V (unless otherwise noted) AC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(CLKIN) CLKIN input frequency External clock 32.100 32.768 33.420 kHz t(CLKIN_HI) CLKIN high time External clock 2 28 µs f(INTERNAL) Internal clock frequency TA = −25°C to 85°C 26.2 32.768 39.4 kHz t(SCDDELAY) SC delay time td(SC) = 0 ms for charge and discharge V(OCD) = 100 mV, SR(50%) to DSG/CHG(50%) delay. No load. 1 10 µs Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION CHG 21 Push-pull output charge FET gate voltage supply CLKIN 16 Digital input that provides an alternate clock with internal 100-k Ω pullup to VREG CNTL 10 Active low input enables CHG, DSG and PCHG. Internal pullup DSG 23 Push-pull output discharge FET gate voltage supply GND 11, 13 Analog ground pin and negative pack terminal LEDOUT 20 Provides current to drive LED capacity display PCHG 22 Push-pull output precharge FET gate voltage supply SCLK 14 Open-drain bidirectional serial interface clock with internal 10-k Ω pullup to VREG SDATA 15 Open-drain bidirectional serial interface data with internal 10-k Ω pullup to VREG SR1 8 Current sense positive terminal when charging relative to SR2 SR2 9 Current sense positive terminal when discharging relative to SR1 TOUT 18 Provides thermistor bias current VBAT 2 Battery positive terminal sense input for regulator shutdown VC1 3 Sense voltage input terminal for most positive cell and balance current input for most positive cell. Connected to VC2 in 3-cell applications VC2 4 Sense voltage input terminal for second most positive cell, balance current input for second most positive cell, and return balance current for most positive cell VC3 5 Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return balance current for second most positive cell VC4 6 Sense voltage input terminal for least positive cell, balance current input for least positive cell, and return balance current for third most positive cell VC5 7 Sense voltage input terminal for most negative cell, return balance current for least positive cell VCC 1 Diode protected BAT+ terminal and primary power source VCELL 12 Output of scaled value of the measured cell voltage VPACK 24 Pack positive terminal and alternate power source VREG 19 Integrated 3.3-V regulator output XALERT 17 Open-drain output used to indicate status register changes. With internal 100 k Ω pullup to VREG |
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