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DS17285S-3 Datasheet(PDF) 7 Page - Dallas Semiconductor

Part # DS17285S-3
Description  3V/5V Real-Time Clock
Download  38 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS17285S-3 Datasheet(HTML) 7 Page - Dallas Semiconductor

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DS17285/DS17287
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RTC ADDRESS MAP
The address map for the RTC registers of the DS17285/DS17287 is shown in Figure 2. The address map
consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and
4 bytes are used for control and status. All registers can be directly written or read except for the
following:
1) Registers C and D are read-only.
2) Bit 7 of Register A is read-only.
3) The high order bit of the second byte is read-only.
Figure 2. DS17285 REAL-TIME CLOCK ADDRESS MAP
TIME, CALENDAR, AND ALARM LOCATIONS
The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.
The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents
of the time, calendar, and alarm registers can be either binary or binary-coded decimal (BCD) format.
Table 1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in
both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and
bank 1 switching is explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written
to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data
format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and
alarm registers must use the same data mode. The set bit in Register B should be cleared after the data
mode bit has been written to allow the real-time clock to update the time and calendar bytes.
Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be
changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents
PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are
double-buffered. Once per second the 10 bytes are advanced by 1 second and checked for an alarm
condition. If a read of the time and calendar data occurs during an update, a problem exists where
seconds, minutes, hours, etc., may not correlate. The probability of reading incorrect time and calendar
data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later
in this text.


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