5

Commercial Temperature Range

IDT72V8980 3.3V Time Slot Interchange

Digital Switch 256 x 256

If the ODE input pin is LOW, then all the serial outputs are high-impedance.

IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)

or disables (if LOW) the output stream and channel.

Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see

Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s

output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on

CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the

CCOoutputistransmittedinLOW. Thecontentsofthe256CCObitsoftheCMH

are transmitted sequentially on to the CCO output pin and are synchronous to

the TX streams. To allow for delay in any external control circuitry the contents

of the CCO bit is output one channel before the corresponding channel on the

TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding

to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's

ofCMHforchannel1ofstreams0-7areoutputsynchronouslywithTXchannel

0 bits 7-0.

INITIALIZATION OF THE IDT72V8980

On initialization or power up, the contents of the Connection Memory High

can be in any state. This is a potentially hazardous condition when multiple TX

TABLE 2 — ADDRESS MAPPING

Connection Memory High

Connection Memory Low

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

Channel 0

Channel 1

Channel 2

Channel 31

100001

100010

111111

Data Memory

0

0

0

0

0

0

1

1

0

1

0

2

0

1

1

3

1

0

0

4

1

0

1

5

1

1

0

6

1

1

1

7

Stream

0

1

1

0

1

1

Control Register

External Address Bits

A5-A0

5705 drw07

100000

The Control Register is only accessed when A5=0.

All other address bits have no effect when A5=0.

When A5 =1, only 32 bytes are randomly accessable

via A0-A4 at any one instant. Which 32 bytes are

accessed is determined by the state of CRb0 -CRb4.

stream.

TABLE 1 — INPUT STREAM TO OUTPUT

STREAM COMBINATIONS THAT CAN

PROVIDE THE MINIMUM 2-CHANNEL

DELAY

Figure 3. Address Mapping

NOTES:

1. Writing to the Control Register is the only fast transaction.

2. Memory and stream are specified by the contents of the Control Register.

A5 A4 A3 A2 A1 A0

HEX ADDRESS

LOCATION

0

XXXXX

00-1F

100000

20

100001

21

••••••

•

•

••••••

•

•

••••••

•

•

111111

3F

outputs are tied together to form matrices. The ODE pin should be held low on

power up to keep all outputs in the high impedance condition until the contents

of the CMH are programmed.

Duringthemicroprocessorinitializationroutine,themicroprocessorshould

programthedesiredactivepathsthroughthematrices,andputallotherchannels

into the high impedance state. Care should be taken that no two connected TX

outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor

controlling the matrices can bring the ODE signal high to relinquish high

impedance state control to the Connection Memory High bits outputs.

RESET

The reset pin is designed to be used with board reset circuitry. During reset

the TX serial streams will be put into high-impedance and the state of internal

registers and counters will be reset. As the connection memory can be in any

state after a power up, the ODE pin should be used to hold the TX streams in

high-impedance until the per-channel output enable control in the connection

memoryhighisappropriatelyprogrammed.ThemaindifferencebetweenODE

and reset is, reset alters the state of the registers and counters where as ODE

controls only the high-impedance state of the TX streams.

RESETinputisonly

provided on the SSOP package.

Input

Output Stream

0

1,2,3,4,5,6,7

1

3,4,5,6,7

2

5,6,7

37

4

1,2,3,4,5,6,7

5

3,4,5,6,7

6

5,6,7

77