Page 5

Enpirion Power Datasheet ES1021QI Power Sequencing Controller

July 2014

Altera Corporation

Pin Descriptions

PIN

NAME

PIN

NUMBER

DESCRIPTION

23

Chip Bias. Bias IC from nominal 1.5V to 5V.

GND

10

Bias Return. IC ground.

ENABLE_1

1

Input to start on/off sequencing. Input to initiate start of programmed sequencing of supplies on or off. Enable functionality disabled for 10ms

after UVLO is satisfied. ES1021QI has two ENABLE inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and ENABLE_2 is for (C, D).

ENABLE_2

11

RESET

24

RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts

low upon UVLO not being satisfied or ENABLE being deasserted. RESET outputs are open-drain, N-channel FET and are guaranteed to be in correct

state for VDD down to 1V and are filtered to ignore fast transients on VDD and UVLO_X.

RESET_2 only exists for (C, D) group I/O.

RESET_2

9

UVLO_A

20

Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout referenced to an internal 0.633V reference. Filtered to ignore short

(<30µs) transients below programmed UVLO level.

UVLO_B

12

UVLO_C

17

UVLO_D

14

DLY_ON_A

21

Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor charged

with 1µA 10ms after turn-on initiated by ENABLE/ENABLE. Internal current source provides delay to associated FET GATE turn-on.

DLY_ON_B

8

DLY_ON_C

16

DLY_ON_D

15

DLY_OFF_A

18

Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground.

Each capacitor charged with 1µA internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus

turning off FET.

DLY_OFF_B

13

DLY_OFF_C

3

DLY_OFF_D

4

GATE_A

2

FET Gate Drive Output. Drives external FETs with 1µA current source to soft-start ramp into load.

GATE_B

5

GATE_C

6

GATE_D

7

GND

EPAD

Ground. Die Substrate. Can be left floating.

NC

19, 22

No Connect

ES1021QI Feature Matrix

PART

NAME

EN/EN

CMOS/

TTL

GATE DRIVE

OR OPEN

DRAIN

OUTPUTS

REQUIRED

CONDITIONS

FOR INITIAL

START-UP

NUMBER OF

UVLO INPUTS

MONITORED BY

EACH RESET

NUMBER OF

CHANNELS THAT

TURN OFF WHEN

ONE UVLO

FAULTS

PRESET OR

ADJUSTABLE

SEQUENCE

NUMBER OF

UVLO AND

PAIRS OF I/O

FEATURES

ES1021QI

EN

CMOS

Gate Drive

4 UVLO

2 EN

2 UVLO

2 Gates

Preset

2 Monitors

with 2 I/O

Dual Redundant

Operation

10128

July 9, 2014

Rev A