NCP4208

http://onsemi.com

5

PIN ASSIGNMENT

Pin No.

Mnemonic

Description

1

VCC3

3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the

interval 3.3 V LDO.

2

PWRGD

Power−Good Output: Open−drain output that signals when the output voltage is outside of the

proper operating range.

3

ALERT

ALERT Output: Open drain output that asserts low when the VR exceeds a programmable limit.

Can be configured for Comparator Mode or Interrupt Mode.

4

SDA

5

SCL

6

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the

PWRGD output low.

7

GND

Ground. All internal biasing and the logic output signals of the device are referenced to this

ground.

8 to 9

NC

No Connect

10

IMON

Total Current Output Pin.

11

IREF

Current Reference Input. An external resistor from this pin to ground sets the reference current for

IFB, and IILIMFS.

12

RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND

sets the oscillator frequency of the device.

13

RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets

the internal PWM ramp.

14

FBRTN

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output

voltage.

15

COMP

Error Amplifier Output and Compensation Point.

16

FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external

resistor between this pin and the output voltage sets the no load offset point.

17

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the

current sense amplifier and the power−good and crowbar functions. This pin should be

connected to the common point of the output inductors.

18

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the

average inductor currents together to measure the total output current.

19

CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM

determines the gain of the current sense amplifier and the positioning loop response time.

20

ILIMFS

Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the

internal current sensing signal for current limit and IMON. This value can be overwritten using

21

ODN

Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low,

otherwise it functions in the same way as OD1.

22

OD1

Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when

VCC is below its UVLO threshold to signal to the Driver IC that the driver high−side and

low−side outputs should go low.

23 to 30

SW8 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of

unused phases should be left open.

31 to 38

PWM8 to PWM1

Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver

such as the ADP3121. Connecting the PWM8, PWM7, PWM6, PWM5, PWM4, PWM3 and

PWM2 outputs to VCC causes that phase to turn off, allowing the NCP4208 to operate as a

1−, 2−, 3−, 4−, 5−, 6−, 7−, or 8−phase controller.

39

VCC

Supply Voltage for the Device. A 340 W resistor should be placed between the 12 V system

supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V.

40 to 47

VID7 to VID0

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic

zero if left open. When in normal operation mode, the DAC output programs the FB regulation

voltage from 0.375 V to 1.6 V.

48

PSI

Power State Indicator. Pulling this pin low places the controller in lower power state operation.