74HC164

Document number: DS36279 Rev. 2- 2

2 of 10

www.diodes.com

March 2015

© Diodes Incorporated

74HC164

400

Pin Descriptions

Mode

Input

Output

MR

CP

DSA

DSB

Q0

Q1-Q7

Reset

L

X

X

X

L

L

Shift

H

↑

L

X

L

Qn←Qn-1 (n= 1 to7)

H

↑

X

L

L

Qn←Qn-1 (n= 1 to7)

H

↑

H

H

H

Qn←Qn-1 (n= 1 to7)

Note:

4. Signals asserted on DSA and DSB must be in place longer than Tsu (set-up time) before CP occurs and remain in place Thold (hold time) after CP.

Logic Diagram

9

MR

8

CP

Q0

D

C

R

Q

3

Q1

D

C

R

Q

4

Q2

D

C

R

Q

5

Q3

D

C

R

Q

6

Q4

D

C

R

Q

10

Q5

D

C

R

Q

11

Q6

D

C

R

Q

12

Q7

D

C

R

Q

13

2

DSB

1

DSA

Pin Number

Pin Name

Function

1

DSA

Serial Data Input

2

DSB

Serial Data Input

3

Q0

Data Output

4

Q1

Data Output

5

Q2

Data Output

6

Q3

Data Output

7

GND

Ground

8

CP

Clock Pulse

–Positive Edge Triggered

9

MR

Master Reset - Asynchronous

10

Q4

Data Output

11

Q5

Data Output

12

Q6

Data Output

13

Q7

Data Output

14

Supply Voltage