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AD7400BRW Datasheet(PDF) 5 Page - Analog Devices

Part # AD7400BRW
Description  Isolated Sigma-Delta Modulator
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7400BRW Datasheet(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
AD7400/AD7401
TIMING SPECIFICATIONS1
Table 3. AD7400/AD7401 Timing Specifications
(VDD1 = VDD2 = 4.5V to 5.5V, TA = TMAX to TMIN unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
FMCLKOUT
10
MHz typ
AD7400
8.2/13.2
MHz min/max
TMCLKIN2
1
MHz min
AD7401
20
MHz max
t13
30
ns max
Data Access Time after MCLK Rising Edge
t23
15
ns min
Data Hold Time after MCLK Rising Edge
t3
0.4 x tMCLKIN
ns max
Master Clock Low Time
t4
0.4 x tMCLKIN
ns max
Master Clock High Time
NOTES
1 Sample tested @ 25 C to ensure compliance. All input signals are specified with tr = tf = 5ns (10% to 90% of VDD1) and timed form a voltage level of 1.6 Volts. See Figure
1.
2 Mark Space ratio for the MCLKIN input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8V or 2.0V.
+1.6V
IOL
200µA
200µA
IOH
TO
OUTPUT
PIN
CL
50pF
Figure 1. Load Circuit for Digital Output Timing Specifications
MCLKIN /
MCLKOUT
MDAT
t1
t2
t3
t4
Figure 2. Data Timing
Rev. PrH | Page 5 of 10


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