ADuC844

REV. PrB

-9-

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTIONS

Pin No:

52-MQFP

Pin No:

56-CSP

Pin

Mnemonic

Type*

Description

1, 2

56, 1

P1.0/P1.1

I/O

P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-

up configuration as described below for Port 3. P1.0 and P1.1 have an increased

current drive sink capability of 10mA.

P1.0 and P1.1 also have various secondary functions as described below.

P1.0/T2/PWM0

I/O

P1.0 can also be used to provide a clock input to Timer 2. When enabled,

counter 2 is incremented in response to a negative transition on the T2 input

pin.

If the PWM is enabled, the PWM0 output will appear at this pin.

P1.1/T2EX/PWM1

I/O

P1.1 can also be used to provide a control input to Timer 2. When enabled, a

negative transition on the T2EX input pin will cause a Timer 2 capture or reload

event.

If the PWM is enabled, the PWM1 output will appear at this pin.

3 à 4

9 à 12

2 à3

11 à14

P1.2 àP1.7

I

Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital

input for which ‘0’ must be written to the port bit. As a digital input, these pins

must be driven high or low externally.

These pins also have the following analog functionality:

P1.2/DAC/IEXC1

I/O

The voltage output from the DAC or one or both current sources (200 uA or 2 x

200 uA) can be configured to appear at this pin.

P1.3/AIN5/IEXC2

I/O

Auxiliary ADC Input or one or both current sources can be configured at this

pin.

P1.4/AIN1

I

Primary ADC, Positive Analog Input

P1.5/AIN2

I

Primary ADC, Negative Analog Input

P1.6/AIN3

I

Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input

P1.7/AIN4/DAC

I/O

Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The

voltage

5

4

AVDD

S

Analog Supply Voltage

6

5

AGND

S

Analog Ground.

N/C

6

AGND

S

A second Analog ground is provided with the CSP version only.

7

7

REFIN-

I

External Reference Input, negative terminal

8

8

REFIN+

I

External Reference Input, positive terminal

13

15

SS

I

The slave select input for the SPI Interface is present at this pin. A weak pull-up

is present on this pin.

14

16

MISO

I

Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this

input pin.

15

17

RESET

I

Reset Input. A high level on this pin for 16 core clock cycles while the

oscillator is running resets the device. There is an internal weak pull-down and

a Schmitt trigger input stage on this pin.