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TPS65052-Q1 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS65052-Q1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 40 page  TPS65050-Q1, TPS65051-Q1, TPS65052-Q1 TPS65054-Q1, TPS65056-Q1 SLVSBJ1A – SEPTEMBER 2012 – REVISED NOVEMBER 2012 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION TPS65050 TPS65051 TPS65052 TPS65054 TPS65056- NAME -Q1 -Q1 -Q1 -Q1 Q1 AGND 2 2 2 2 2 I Analog GND, connect to PGND and thermal pad BP 1 1 1 1 1 I Input for bypass capacitor for internal reference TPS65050-Q1 and TPS65051-Q1: Feedback pin for converter 2. Connect DEFDCDC2 to the center of the external resistor divider. TPS65052-Q1 and TPS65056-Q1: Select pin of converter 2 output DEFDCDC2 17 17 17 17 17 I voltage. High = 1.3 V, Low = 1 V TPS65054-Q1: Select pin of converter 2 output voltage. High = 1.05 V, Low = 1.3 V Digital input, used to set the default output voltage of LDO1 to DEFLDO1 31 -- 31 -- -- I LDO4; LSB Digital input, used to set the default output voltage of LDO1 to DEFLDO2 6 -- 6 -- -- I LDO4 Digital input, used to set the default output voltage of LDO1 to DEFLDO3 9 -- 9 -- -- I LDO4 Digital input, used to set the default output voltage of LDO1 to DEFLDO4 13 -- 13 -- -- I LDO4; MSB EN_DCDC1 25 25 25 25 25 I Enable input for converter 1, active-high EN_DCDC2 26 26 26 26 26 I Enable input for converter 2, active-high Enable input for LDO1. Logic high enables the LDO, logic low EN_LDO1 27 27 27 27 27 I disables the LDO. Enable input for LDO2. Logic high enables the LDO, logic low EN_LDO2 28 28 28 28 28 I disables the LDO. Enable input for LDO3. Logic high enables the LDO, logic low EN_LDO3 15 15 15 15 15 I disables the LDO. Enable input for LDO4. Logic high enables the LDO, logic low EN_LDO4 16 16 16 16 16 I disables the LDO. FB1 -- 31 -- 31 31 I Feedback input for the external voltage divider FB2 -- 6 -- 6 6 I Feedback input for the external voltage divider FB3 -- 9 -- 9 9 I Feedback input for the external voltage divider FB4 -- 13 -- 13 13 I Feedback input for the external voltage divider Input to adjust output voltage of converter 1 between 0.6 V and VI. FB_DCDC1 24 24 24 24 24 I Connect an external resistor divider between VOUT1, this pin, and GND. GND 8 -- -- -- -- - Connect to GND HYSTERESIS -- 8 8 8 8 I Input for hysteresis on reset threshold L1 22 22 22 22 22 O Switch pin of converter 1. Connected to inductor L2 20 20 20 20 20 O Switch pin of converter 2. Connected to inductor Select between power-safe mode and forced-PWM mode for DCDC1 and DCDC2. In power-safe mode, the device uses PFM at MODE 32 32 32 32 32 I light loads, PWM for higher loads. Setting this pin to high level selects forced-PWM mode. If this pin has low level, then the device operates in power-safe mode. PB_IN 7 -- -- -- -- I Input for the pushbutton ON-OFF function Open-drain output. Active-low after the supply voltage (VCC) PB_OUT 14 -- -- -- -- O exceeds the undervoltage-lockout threshold. Toggle the pin by pulling PB_IN high. PGND1 23 23 23 23 23 I GND for converter 1 PGND2 19 19 19 19 19 I GND for converter 2 RESET -- 14 14 14 14 O Open-drain active-low reset output, 100-ms reset-delay time THRESHOLD -- 7 7 7 7 I Reset input Power supply for digital and analog circuitry of DCDC1, DCDC2 VCC 3 3 3 3 3 I and LDOs. Connect this pin to the same voltage supply as VINDCDC1/2. Feedback voltage-sense input, connect directly to the output of VDCDC2 18 18 18 18 18 I converter 2. Input voltage for VDCDC1 and VDCDC2 step-down converters. VINDCDC1/2 21 21 21 21 21 I Connect this pin to the same voltage supply as VCC. VINLDO1 29 29 29 29 29 I Input voltage for LDO1 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS65051-Q1 |
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