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TPS65132T6YFFT Datasheet(PDF) 10 Page - Texas Instruments |
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TPS65132T6YFFT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 64 page  tf tLOW tr thd;STA thd;DAT tsu;DAT tf HIGH tsu;STA S Sr P S thd;STA tr tBUF tsu;STO SDA SCL TPS65132 SLVSBM1G – JUNE 2013 – REVISED AUGUST 2015 www.ti.com 7.6 I 2C Interface Timing Requirements / Characteristics (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standard mode 100 kHz fSCL SCL clock frequency Fast mode 400 kHz Standard mode 4.7 µs tLOW LOW period of the SCL clock Fast mode 1.3 µs Standard mode 4.0 µs tHIGH HIGH period of the SCL clock Fast mode 600 ns Standard mode 4.7 µs tBUF Bus free time between a STOP and START condition Fast mode 1.3 µs Standard mode 4.0 µs thd;STA Hold time for a repeated START condition Fast mode 600 ns Standard mode 4.7 µs tsu;STA Setup time for a repeated START condition Fast mode 600 ns Standard mode 250 ns tsu;DAT Data setup time Fast mode 100 ns Standard mode 0.05 3.45 µs thd;DAT Data hold time Fast mode 0.05 0.9 µs Standard mode 20 + 1000 ns 0.1CB Rise time of SCL signal after a repeated START condition tRCL1 and after an acknowledge bit Fast mode 20 + 1000 ns 0.1CB Standard mode 20 + 1000 ns 0.1CB tRCL Rise time of SCL signal Fast mode 20 + 300 ns 0.1CB Standard mode 20 + 300 ns 0.1CB tFCL Fall time of SCL signal Fast mode 20 + 300 ns 0.1CB Standard mode 20 + 1000 ns 0.1CB tRDA Rise time of SDA signal Fast mode 20 + 300 ns 0.1CB Standard mode 20 + 300 ns 0.1CB tFDA Fall time of SDA signal Fast mode 20 + 300 ns 0.1CB Standard mode 4.0 µs tsu;STO Setup time for STOP condition Fast mode 600 ns CB Capacitive load for SDA and SCL 0.4 nF (1) Industry standard I2C timing characteristics acoording to I2C-Bus Specification, Version 2.1, January 2000. Not tested in production. Figure 1. Serial Interface Timing For F/S-Mode 10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65132 |
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