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BQ76PL455A Datasheet(PDF) 11 Page - Texas Instruments |
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BQ76PL455A Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 125 page  11 bq76PL455A www.ti.com SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated ADC: AUXn General Purpose Inputs (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDCL_AUX DC Leakage Current Channel not selected for conversion, TESTAUXPU = 0 < ±0.1 µA RIN_AUX (1) Equivalent input resistance Channel selected In Acquisition Mode > 3 M Ω CAUX (1) Input capacitance Channel selected 30 pF RAUX_PU Internal switched pull-up resistor per AUXn input, supplied from VP pin TESTAUXPU[n] = 1; n = 0 to 7 18 26 46 k Ω (1) Specified from characterization data, not tested in production. (2) Specified by design, not tested in production. 6.14 ADC: Internal Temperature Measurement and Thermal Shutdown (TSD) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TINT_AD (1) Internal temperature accuracy of analog die –7 3 13 °C TINT_DD (1) Internal temperature accuracy of digital die –34 8 54 °C TSDT (2) Thermal shutdown, junction temperature both analog and digital dies Increasing temperature 115 140 °C (1) For more functional information, see Passive Balancing . (2) In the event of an open wire condition, if TSTCONFIG[EQ_SQUEEZE_EN] = 1 and this causes EQVMIN to be violated, it may be necessary to power down the device to disable the squeeze resistor. (3) VSENSE1 minimum voltage required for correct operation of any or all EQn outputs. If VSENSE1 falls below this value, any or all other EQ outputs may fail to assert when requested. The opposite is not true. Outputs will not assert unintentionally when set to the OFF state. 6.15 Passive Balancing Control Outputs PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT EQSR_OFF Output resistance, internally in series with driver EQn = 0 (OFF) 1.2 1.5 1.8 kΩ EQSR_ON EQn = 1 (ON) 1.9 2.3 2.9 kΩ EQVMIN (2) Cell voltage required for balancing 1.8 V VS1MIN VSENSE1 minimum voltage for balancing(3) 1.8 V (1) Specified by design, not tested in production. (2) Defaults: RX = TX = 250 kBd at communications RESET or (factory set) EEPROM setting at POR. (3) Discrete rates only, not continuously variable. 6.16 Digital Input/Output: VIO-Based Single-Ended I/O PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Logic-level output-voltage high FAULT_N, TX, GPIO ILOAD = 5 mA VIO – 0.7 VIO V VOL Logic-level output-voltage low FAULT_N, TX, GPIO ILOAD = 5 mA DGND 0.7 V VIH Logic-level input-voltage high RX, GPIO VIO – 0.7 V VIL Logic-level input-voltage low RX, GPIO 0.7 V CDIG_IN Input Capacitance(1) RX, GPIO 5 pF RPU GPIO0..5 pull-up resistor 13 17 25 kΩ RPD GPIO0..5 pull-down resistor 16 22 31 kΩ ILKG Input leakage source/sink current RX, GPIOx < ±1 µA RXTXBAUD RX/TX signaling rate(2)(3) 125 1000 Kbaud ERRBAUD_RX Input Baud rate error(1) –3% 3% ERRBAUD_TX Output Baud rate error(1) –1.5% 1.5% tCOMM_BREAK Communications Clear (Break)(1) 10 15 bit periods tCOMM_RESET Communications Reset(1) 200 µs |
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