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UCD90160ARGCT Datasheet(PDF) 7 Page - Texas Instruments |
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UCD90160ARGCT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 59 page  7 UCD90160A www.ti.com SLVSDD4 – SEPTEMBER 2016 Product Folder Links: UCD90160A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins. (2) The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. (3) The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SUPPLY CURRENT IV33A Supply current(1) VV33A = 3.3 V 8 mA IV33DIO VV33DIO = 3.3 V 2 mA IV33D VV33D = 3.3 V 40 mA IV33D VV33D = 3.3 V, storing configuration parameters in flash memory 50 mA ANALOG INPUTS (MON1–MON16) VMON Input voltage range MON1–MON13 0 2.5 V MON14–MON16 0.2 2.5 V INL ADC integral nonlinearity –4 4 LSB DNL ADC differential nonlinearity -2 2 LSB Ilkg Input leakage current 3 V applied to pin 100 nA IOFFSET Input offset current 1-k Ω source impedance –5 5 μA RIN Input impedance MON1–MON13, ground reference 8 MΩ MON14–MON16, ground reference 0.5 1.5 3 M Ω CIN Input capacitance 10 pF tCONVERT ADC sample period 16 voltages sampled, 3.89 μsec/sample 400 μsec VREF ADC 2.5 V, internal reference accuracy 0°C to 125°C –0.5% 0.5% –40°C to 125°C –1% 1% ANALOG INPUT (PMBUS_ADDRx) IBIAS Bias current for PMBus Addr pins 9 11 μA VADDR_OPEN Voltage – open pin PMBUS_ADDR0, PMBUS_ADDR1 open 2.26 V VADDR_SHORT Voltage – shorted pin PMBUS_ADDR0, PMBUS_ADDR1 short to ground 0.124 V DIGITAL INPUTS AND OUTPUTS VOL Low-level output voltage IOL = 6 mA (2), V 33DIO = 3 V Dgnd + 0.25 V VOH High-level output voltage IOH = –6 mA (3), V 33DIO = 3 V V33DIO – 0.6 V VIH High-level input voltage V33DIO = 3 V 2.1 3.6 V VIL Low-level input voltage V33DIO = 3.5 V 1.4 V MARGINING OUTPUTS TPWM_FREQ MARGINING-PWM frequency FPWM1-8 15.260 125000 kHz PWM3-4 0.001 7800 DUTYPWM MARGINING-PWM duty cycle range 0% 100% SYSTEM PERFORMANCE VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms VRESET Supply voltage at which device comes out of reset For power-on reset (POR) 2.4 V tRESET Low-pulse duration needed at RESET pin To reset device during normal operation 2 μS f(PCLK) Internal oscillator frequency TA = 125°C, TA = 25°C 240 250 260 MHz tretention Retention of configuration parameters TJ = 25°C 100 Years Write_Cycles Number of nonvolatile erase/write cycles TJ = 25°C 20 K cycles |
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