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DS17485S-3 Datasheet(PDF) 4 Page - Dallas Semiconductor |
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DS17485S-3 Datasheet(HTML) 4 Page - Dallas Semiconductor |
4 / 38 page DS17485/DS17487 4 of 38 WR – RTC Write Input; Active Low. The WR signal is an active low signal. The WR signal defines the time period during which data is written to the addressed register. CS – RTC Chip-Select Input; Active Low. The chip select signal must be asserted low during a bus cycle for DS17485/DS17487 to be accessed. CS must be kept in the active state during RD and WR timing. Bus cycles that take place with ALE asserted but without asserting CS latches addresses. However, no data transfer occurs. IRQ – Interrupt Request Output; Open Drain, Active Low. The IRQ pin is an active low output of the DS17485/DS17487 that can be tied to the interrupt input of a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active state. When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ pin is an open-drain output and requires an external pullup resistor. The voltage on the pullup supply should be no greater than VCC + 0.2V. PWR – Power-On Output; Open-Drain, Active Low. The PWR pin is intended for use as an on/off control for the system power. With VCC voltage removed from the DS17485/DS17487, PWR can be automatically activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the system is powered on, the state of PWR can be controlled by bits in the Dallas registers. The PWR pin can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup supply should be no greater than 3.9V. KS – Kickstart Input; Active Low. When VCC is removed from the DS17485/DS17487, the system can be powered on in response to an active low transition on the KS pin, as might be generated from a key closure. VBAUX must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the kickstart function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin can be used as an interrupt input. RCLR – RAM Clear Input; Active Low. If enabled by software, taking RCLR low results in the clearing of the 114 bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is present. RCLR has an internal pullup and should not be connected to an external pullup resistor. VBAUX – Auxiliary battery input required for kickstart and wake-up features. This input also supports clock/calendar and user RAM if VBAT is at lower voltage or is not present. A standard +3V lithium cell or other energy source can be used. For 3V operation, VBAUX must be held between +2.5V and +3.7V. For 5V operation, VBAUX must be held between +2.5V and +5.2V. If VBAUX is not going to be used it should be grounded and the auxiliary-battery-enable bit bank 1, register 4BH, should = 0. UL recognized to ensure against reverse charging current when used with a lithium battery. See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm. |
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