TPS786

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SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015

6.4 Thermal Information

DRB (SON)

DCQ (S0T-223)

KTT (TO-263)

UNIT

8 PINS

6 PINS

5 PINS

Junction-to-ambient thermal resistance

41.1

54.2

40.7

°C/W

Junction-to-case (top) thermal resistance

49.1

33.3

43.1

°C/W

Junction-to-board thermal resistance

16.6

8.9

21.5

°C/W

Junction-to-top characterization parameter

0.7

2.6

9.4

°C/W

Junction-to-board characterization parameter

16.8

8.8

20

°C/W

Junction-to-case (bottom) thermal resistance

5.2

N/A

2.1

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as

specified in the JESD51 series. The following assumptions are used in the simulations:

(a)

i. DRB: The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array.

(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper

coverage.

coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper

area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction

Temperature sections of this data sheet.

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