Data Sheet

8

Rev. 1.0, 2012-11-08

TLF1963

General Product Characteristics

4.2

Functional Range

Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the Electrical Characteristics table.

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 2

Functional Range

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Max.

4.2.1

Input voltage

V

I

2.5

20

V

–

4.2.2

Output Capacitor’s Requirements

for Stability

C

Q

10

–

µF

1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

ESR(C

–3

Ω

2) relevant ESR value at

4.2.3

Junction temperature

T

j

-40

150

°C

Table 3

Thermal Resistance

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

Package PG-TO263-5

4.3.1

1) Not subject to production test, specified by design.

R

thJC

–

0.84

–

K/W

measured to heat

slug

4.3.2

Junction to Ambient1)

R

thJA

–19

–

K/W

2)

2) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4.3.3

–

64

–

K/W

3) Specified

R

(Chip+Package) was simulated on a 76.2

4.3.4

–

36

–

K/W

300 mm² heatsink

area3)

4.3.5

–

29

–

K/W

600 mm² heatsink

area3)

Package PG-TO252-5

4.3.6

Junction to Case1)

R

thJC

–

0.78

–

K/W

measured to heat

slug

4.3.7

Junction to Ambient1)

R

thJA

–24

–

K/W

2)

4.3.8

–

95

–

K/W

footprint only3)

4.3.9

–

50

–

K/W

300 mm² heatsink

area3)

4.3.10

–

38

–

K/W

600 mm² heatsink

area3)